Dominick.Vansevenant/Zorro-LAN-IDE
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Z2-Firmware with working CP and LAN

Browse Source
This commit is contained in:
MHeinrichs
2019-02-21 13:53:40 +01:00
parent 11c25fe78d
commit 5fc99a4460
140 changed files with 49227 additions and 28406 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Logic/LAN_IDE/LAN_IDE_CP.syr
+46 -50
View File
@@ -55,7 +55,7 @@ XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Goal : Area
Optimization Effort : 1
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
@@ -91,7 +91,6 @@ Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <beh
* HDL Analysis *
=========================================================================
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
INFO:Xst:2679 - Register <AUTOCONFIG_Z3_ACCESS> in unit <LAN_IDE_CP> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
@@ -112,15 +111,13 @@ Synthesizing Unit <LAN_IDE_CP>.
Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <SHUT_UP_Z2<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <AUTOCONFIG_Z3_ACCESS> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found finite state machine <FSM_0> for signal <LAN_SM>.
-----------------------------------------------------------------------
| States | 12 |
| Transitions | 17 |
| Inputs | 3 |
| Outputs | 12 |
| States | 13 |
| Transitions | 19 |
| Inputs | 4 |
| Outputs | 14 |
| Clock | CLK_EXT (rising_edge) |
| Reset | LAN_SM_RST (positive) |
| Reset type | asynchronous |
@@ -168,31 +165,30 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit tristate buffer for signal <A<10>>.
Found 1-bit tristate buffer for signal <A<9>>.
Found 1-bit tristate buffer for signal <A<8>>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 178.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 177.
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE>.
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE_CYCLE>.
Found 1-bit register for signal <AUTOCONFIG_Z2_ACCESS>.
Found 1-bit register for signal <CONFIG_READY>.
Found 1-bit register for signal <CP_ACCESS>.
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 292.
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 290.
Found 8-bit register for signal <CP_BASEADR>.
Found 1-bit register for signal <CP_RD_S>.
Found 1-bit register for signal <CP_WE_QUIRK>.
Found 1-bit register for signal <CP_WE_S>.
Found 4-bit register for signal <D_Z2_OUT>.
Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 645.
Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 638.
Found 16-bit register for signal <DQ_DATA>.
Found 1-bit register for signal <DQ_SWAP>.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 263.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 261.
Found 1-bit register for signal <IDE_ACCESS>.
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 299.
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 297.
Found 8-bit register for signal <IDE_BASEADR>.
Found 1-bit register for signal <IDE_ENABLE>.
Found 1-bit register for signal <IDE_R_S>.
Found 1-bit register for signal <IDE_W_S>.
Found 14-bit register for signal <LAN_A_INIT>.
Found 1-bit register for signal <LAN_ACCESS>.
Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 262.
Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 260.
Found 16-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_CS_RST>.
Found 16-bit register for signal <LAN_D_INIT>.
@@ -201,13 +197,13 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit register for signal <LAN_IRQ_OUT>.
Found 1-bit register for signal <LAN_RD_S>.
Found 1-bit register for signal <LAN_READY>.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 406.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 387.
Found 1-bit register for signal <LAN_SM_RST>.
Found 1-bit register for signal <LAN_WR_RST>.
Found 1-bit register for signal <LAN_WRH_S>.
Found 1-bit register for signal <LAN_WRL_S>.
Found 1-bit register for signal <ROM_OE_S>.
Found 2-bit register for signal <SHUT_UP_Z2<1:0>>.
Found 3-bit register for signal <SHUT_UP_Z2>.
Found 1-bit register for signal <Z3_A_LOW>.
Found 14-bit register for signal <Z3_ADR>.
Found 32-bit register for signal <Z3_DATA>.
@@ -267,17 +263,18 @@ Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:4]> with compact encoding.
-------------------------------
nop | 0000
start_read_upper | unreached
wait_read_upper | 0101
end_read_upper | 1110
start_read_lower | 0001
wait_read_lower | 0011
end_read_lower | 0010
start_write_upper | 1101
wait_write_upper | 0111
end_write_upper | 0110
start_write_lower | 1001
wait_write_lower | 1011
end_write_lower | 1010
wait_read_upper | 0001
end_read_upper | 1010
start_read_lower | 0101
wait_read_lower | 0111
end_read_lower | 0110
start_write_upper | 1001
wait_write_upper | 0011
end_write_upper | 0010
start_write_lower | 1101
wait_write_lower | 1111
end_write_lower | 1110
config_rw | 0100
-------------------------------
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <13>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <12>. This FF/Latch will be trimmed during the optimization process.
@@ -344,10 +341,12 @@ INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent t
INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_4> <LAN_D_INIT_9>
Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=s : SHUT_UP_Z2_0
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
implementation constraint: INIT=s : SHUT_UP_Z2_2
implementation constraint: INIT=s : SHUT_UP_Z2_1
implementation constraint: INIT=s : SHUT_UP_Z2_0
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
implementation constraint: INIT=r : LAN_INT_ENABLE
implementation constraint: INIT=s : D_Z2_OUT_3
implementation constraint: INIT=s : LAN_A_INIT_3
implementation constraint: INIT=s : D_Z2_OUT_2
@@ -358,8 +357,8 @@ Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=r : LAN_D_INIT_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
implementation constraint: INIT=r : LAN_D_INIT_8
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
@@ -386,7 +385,7 @@ Final Results
RTL Top Level Output File Name : LAN_IDE_CP.ngr
Top Level Output File Name : LAN_IDE_CP
Output Format : NGC
Optimization Goal : Speed
Optimization Goal : Area
Keep Hierarchy : Yes
Target Technology : XC9500XL CPLDs
Macro Preserve : YES
@@ -398,23 +397,20 @@ Design Statistics
# IOs : 117
Cell Usage :
# BELS : 1283
# AND2 : 418
# AND3 : 44
# AND4 : 15
# AND5 : 1
# AND8 : 4
# BELS : 989
# AND2 : 369
# AND3 : 16
# GND : 1
# INV : 451
# OR2 : 277
# OR3 : 20
# OR4 : 2
# XOR2 : 50
# INV : 288
# OR2 : 263
# OR3 : 16
# OR4 : 3
# XOR2 : 33
# FlipFlops/Latches : 141
# FD : 4
# FDC : 21
# FDC : 20
# FDCE : 7
# FDP : 41
# FDP : 42
# FDPE : 68
# IO Buffers : 115
# IBUF : 24
@@ -425,13 +421,13 @@ Cell Usage :
Total REAL time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 18.77 secs
-->
Total memory usage is 4534760 kilobytes
Total memory usage is 4534808 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 48 ( 0 filtered)
Number of infos : 11 ( 0 filtered)
Number of warnings : 46 ( 0 filtered)
Number of infos : 10 ( 0 filtered)