Testbench added
This commit is contained in:
@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.09 secs
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Total CPU time to Xst completion: 0.11 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.09 secs
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Total CPU time to Xst completion: 0.11 secs
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--> Reading design: LAN_IDE_CP.prj
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@@ -76,7 +76,8 @@ wysiwyg : NO
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work.
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Architecture behavioral of Entity lan_ide_cp is up to date.
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Entity <lan_ide_cp> compiled.
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Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
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=========================================================================
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* Design Hierarchy Analysis *
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@@ -88,8 +89,6 @@ Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <beh
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* HDL Analysis *
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=========================================================================
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Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
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WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" line 131: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
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<AS>
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Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
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@@ -98,6 +97,7 @@ Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
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=========================================================================
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Performing bidirectional port resolution...
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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Synthesizing Unit <LAN_IDE_CP>.
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Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
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@@ -105,12 +105,9 @@ WARNING:Xst:647 - Input <DS0> is never used. This port will be preserved and lef
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WARNING:Xst:647 - Input <DS1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <FCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1306 - Output <MTACK> is never assigned.
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WARNING:Xst:647 - Input <LAN_INT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <CP_IRQ> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <Z3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <CLK_EXT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:646 - Signal <LAN_INT_ENABLE> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <LAN_INT_D0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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Found 16-bit tristate buffer for signal <D>.
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@@ -123,33 +120,34 @@ WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 120.
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Found 2-bit register for signal <AUTO_CONFIG_DONE>.
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Found 2-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
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Found 2-bit adder for signal <AUTO_CONFIG_DONE_CYCLE$share0000> created at line 251.
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Found 2-bit adder for signal <AUTO_CONFIG_DONE_CYCLE$share0000> created at line 253.
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Found 1-bit register for signal <autoconfig>.
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Found 2-bit comparator less for signal <autoconfig$cmp_lt0000> created at line 133.
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Found 1-bit register for signal <cp>.
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Found 8-bit comparator equal for signal <cp$cmp_eq0000> created at line 146.
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Found 8-bit comparator equal for signal <cp$cmp_eq0001> created at line 137.
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Found 8-bit comparator equal for signal <cp$cmp_eq0002> created at line 142.
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Found 2-bit comparator less for signal <cp$cmp_lt0000> created at line 133.
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Found 8-bit register for signal <CP_BASEADR>.
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Found 1-bit register for signal <CP_RD_S>.
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Found 1-bit register for signal <CP_WE_S>.
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Found 4-bit register for signal <Dout1>.
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Found 2-bit comparator less for signal <Dout1$cmp_lt0000> created at line 253.
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Found 3-bit comparator less for signal <Dout1$cmp_lt0000> created at line 255.
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Found 1-bit register for signal <DS_D>.
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Found 1-bit register for signal <ide>.
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Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 152.
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Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 147.
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Found 8-bit register for signal <IDE_BASEADR>.
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Found 1-bit register for signal <IDE_ENABLE>.
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Found 1-bit register for signal <IDE_R_S>.
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Found 1-bit register for signal <IDE_W_S>.
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Found 1-bit register for signal <lan>.
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Found 8-bit comparator equal for signal <lan$cmp_eq0000> created at line 140.
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Found 1-bit register for signal <lan_adr>.
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Found 8-bit register for signal <LAN_BASEADR>.
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Found 1-bit register for signal <LAN_INT_ENABLE>.
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Found 1-bit register for signal <LAN_RD_S>.
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Found 1-bit register for signal <LAN_WRH_S>.
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Found 1-bit register for signal <LAN_WRL_S>.
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Found 1-bit register for signal <ROM_OE_S>.
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Found 3-bit register for signal <SHUT_UP>.
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Summary:
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inferred 5 D-type flip-flop(s).
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inferred 6 D-type flip-flop(s).
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inferred 1 Adder/Subtractor(s).
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inferred 5 Comparator(s).
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inferred 1 Xor(s).
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@@ -163,13 +161,14 @@ HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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2-bit adder : 1
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# Registers : 23
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1-bit register : 17
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# Registers : 24
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1-bit register : 18
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2-bit register : 2
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4-bit register : 1
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8-bit register : 3
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# Comparators : 5
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2-bit comparator less : 2
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2-bit comparator less : 1
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3-bit comparator less : 1
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8-bit comparator equal : 3
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# Tristates : 10
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1-bit tristate buffer : 8
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@@ -190,8 +189,8 @@ Advanced HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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2-bit adder : 1
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# Registers : 5
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Flip-Flops : 5
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# Registers : 6
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Flip-Flops : 6
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# Comparators : 3
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8-bit comparator equal : 3
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@@ -233,21 +232,22 @@ Design Statistics
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# IOs : 116
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Cell Usage :
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# BELS : 414
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# AND2 : 97
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# AND3 : 9
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# BELS : 437
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# AND2 : 103
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# AND3 : 11
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# AND4 : 1
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# GND : 1
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# INV : 153
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# OR2 : 120
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# OR3 : 5
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# OR4 : 3
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# INV : 164
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# OR2 : 125
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# OR3 : 4
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# OR4 : 2
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# XOR2 : 26
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# FlipFlops/Latches : 49
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# FlipFlops/Latches : 50
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# FD : 9
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# FDC : 4
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# FDCE : 36
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# IO Buffers : 106
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# IBUF : 33
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# FDCE : 37
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# IO Buffers : 109
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# IBUF : 36
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# IOBUFE : 32
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# OBUF : 33
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# OBUFE : 8
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@@ -255,13 +255,13 @@ Cell Usage :
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Total REAL time to Xst completion: 8.00 secs
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Total CPU time to Xst completion: 7.55 secs
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Total CPU time to Xst completion: 7.84 secs
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-->
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Total memory usage is 293716 kilobytes
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Total memory usage is 293704 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 13 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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Number of warnings : 9 ( 0 filtered)
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Number of infos : 1 ( 0 filtered)
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