Dominick.Vansevenant/Zorro-LAN-IDE
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to much logic!

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This commit is contained in:
MHeinrichs
2016-12-28 20:57:10 +01:00
parent 9e20fea5db
commit 53aacaf617
106 changed files with 13289 additions and 16053 deletions
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Logic/LAN_IDE/webtalk_pn.xml
+6 -4
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@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Wed Dec 28 00:49:59 2016">
<application name="pn" timeStamp="Wed Dec 28 20:28:27 2016">
<section name="Project Information" visible="false">
<property name="ProjectID" value="D176CAD312EA42C990C709B74E81AC07" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
@@ -12,16 +12,17 @@ This means code written to parse this file will need to be revisited each subseq
</section>
<section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_LastAppliedStrategy" value="area;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthOpt" value="Area" type="process"/>
<property name="PROP_SynthOptEffort" value="High" type="process"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_UserBrowsedStrategyFiles" value="C:/Xilinx/14.6/ISE_DS/ISE/data/default.xds" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2016-12-13T21:04:49" type="design"/>
<property name="PROP_intWbtProjectID" value="D176CAD312EA42C990C709B74E81AC07" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
@@ -30,6 +31,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_xilxSynthMaxFanout" value="100000" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="XC9500XL CPLDs" type="design"/>
<property name="PROP_xstSafeImplement" value="Yes" type="process"/>
<property name="PROP_DevDevice" value="xc95144xl" type="design"/>
<property name="PROP_DevFamilyPMName" value="xc9500xl" type="design"/>
<property name="PROP_DevPackage" value="TQ144" type="design"/>