Starting the init routiune
This commit is contained in:
MHeinrichs
@@ -0,0 +1,54 @@
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/*********************************************************************
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*
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* Compiler and hardware specific definitions
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||||
*
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*********************************************************************
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* FileName: Compiler.h
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* Dependencies: None
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* Processor: PIC18, PIC24F, PIC24H, dsPIC30F, dsPIC33F, PIC32
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* Compiler: Microchip C32 v1.00 or higher
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* Microchip C30 v3.01 or higher
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||||
* Microchip C18 v3.13 or higher
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* HI-TECH PICC-18 STD 9.50PL3 or higher
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||||
* Company: Microchip Technology, Inc.
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||||
*
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||||
* Software License Agreement
|
||||
*
|
||||
* Copyright (C) 2002-2008 Microchip Technology Inc. All rights
|
||||
* reserved.
|
||||
*
|
||||
* Microchip licenses to you the right to use, modify, copy, and
|
||||
* distribute:
|
||||
* (i) the Software when embedded on a Microchip microcontroller or
|
||||
* digital signal controller product ("Device") which is
|
||||
* integrated into Licensee's product; or
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||||
* (ii) ONLY the Software driver source files ENC28J60.c and
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* ENC28J60.h ported to a non-Microchip device used in
|
||||
* conjunction with a Microchip ethernet controller for the
|
||||
* sole purpose of interfacing with the ethernet controller.
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||||
*
|
||||
* You should refer to the license agreement accompanying this
|
||||
* Software for additional information regarding your rights and
|
||||
* obligations.
|
||||
*
|
||||
* THE SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT
|
||||
* WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT
|
||||
* LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
* MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
|
||||
* BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE
|
||||
* THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER
|
||||
* SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT
|
||||
* (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE.
|
||||
*
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||||
*
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||||
* Author Date Comment
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||||
*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* Howard Schlunder 10/03/2006 Original, copied from old Compiler.h
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* Howard Schlunder 11/07/2007 Reorganized and simplified
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********************************************************************/
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#ifndef __COMPILER_H
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#define __COMPILER_H
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#endif
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@@ -0,0 +1,692 @@
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/*********************************************************************
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*
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* ENC424J600/624J600 Registers and Bits
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*
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*********************************************************************
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* FileName: ENCX24J600.h
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* Dependencies: None
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* Processor: PIC18, PIC24F, PIC24H, dsPIC30F, dsPIC33F, PIC32
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* Compiler: Microchip C32 v1.05 or higher
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* Microchip C30 v3.12 or higher
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* Microchip C18 v3.30 or higher
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* HI-TECH PICC-18 PRO 9.63PL2 or higher
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* Company: Microchip Technology, Inc.
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*
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||||
* Software License Agreement
|
||||
*
|
||||
* Copyright (C) 2002-2009 Microchip Technology Inc. All rights
|
||||
* reserved.
|
||||
*
|
||||
* Microchip licenses to you the right to use, modify, copy, and
|
||||
* distribute:
|
||||
* (i) the Software when embedded on a Microchip microcontroller or
|
||||
* digital signal controller product ("Device") which is
|
||||
* integrated into Licensee's product; or
|
||||
* (ii) ONLY the Software driver source files ENC28J60.c, ENC28J60.h,
|
||||
* ENCX24J600.c and ENCX24J600.h ported to a non-Microchip device
|
||||
* used in conjunction with a Microchip ethernet controller for
|
||||
* the sole purpose of interfacing with the ethernet controller.
|
||||
*
|
||||
* You should refer to the license agreement accompanying this
|
||||
* Software for additional information regarding your rights and
|
||||
* obligations.
|
||||
*
|
||||
* THE SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT
|
||||
* WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT
|
||||
* LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
* MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
|
||||
* BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE
|
||||
* THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER
|
||||
* SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT
|
||||
* (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE.
|
||||
*
|
||||
*
|
||||
* Author Date Comment
|
||||
*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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||||
* Howard Schlunder 11/30/07 Original
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||||
********************************************************************/
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#ifndef __ENCX24J600_H
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#define __ENCX24J600_H
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//#include "GenericTypeDefs.h"
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//#include "HardwareProfile.h"
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#define ENC100_INTERFACE_MODE 3
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// Define macro for 8-bit PSP SFR address translation to SPI addresses
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#define ENC100_TRANSLATE_TO_PIN_ADDR(a) (a)
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#define ENC100_RAM_SIZE (24*1024)
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// Crypto memory addresses. These are accessible by the DMA only and therefore
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// have the same addresses no matter what MCU interface is being used (SPI,
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// 8-bit PSP, or 16-bit PSP)
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#define ENC100_MODEX_Y (0x7880)
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#define ENC100_MODEX_E (0x7800)
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#define ENC100_MODEX_X (0x7880)
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#define ENC100_MODEX_M (0x7900)
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#define ENC100_HASH_DATA_IN (0x7A00)
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#define ENC100_HASH_IV_IN (0x7A40)
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#define ENC100_HASH_LEN_IN (0x7A54)
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#define ENC100_HASH_DIGEST_OUT (0x7A70)
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#define ENC100_HASH_LEN_OUT (0x7A84)
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#define ENC100_HASH_BASE_ADDR (0x7A00)
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#define ENC100_AES_KEY (0x7C00)
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#define ENC100_AES_TEXTA (0x7C20)
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#define ENC100_AES_TEXTB (0x7C30)
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#define ENC100_AES_XOROUT (0x7C40)
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#define SET_OFFSET ENC100_TRANSLATE_TO_PIN_ADDR(0x0100)
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#define CLR_OFFSET ENC100_TRANSLATE_TO_PIN_ADDR(0x0180)
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////////////////////////////////////////////////////
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// ENC424J600/624J600 register addresses //
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////////////////////////////////////////////////////
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// SPI Bank 0 registers --------
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#define ETXST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E00)
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#define ETXSTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E00)
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#define ETXSTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E01)
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#define ETXLEN ENC100_TRANSLATE_TO_PIN_ADDR(0x7E02)
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#define ETXLENL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E02)
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#define ETXLENH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E03)
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#define ERXST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E04)
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#define ERXSTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E04)
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#define ERXSTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E05)
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#define ERXTAIL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E06)
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#define ERXTAILL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E06)
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#define ERXTAILH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E07)
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#define ERXHEAD ENC100_TRANSLATE_TO_PIN_ADDR(0x7E08)
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#define ERXHEADL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E08)
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#define ERXHEADH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E09)
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#define EDMAST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0A)
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#define EDMASTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0A)
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#define EDMASTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0B)
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#define EDMALEN ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0C)
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#define EDMALENL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0C)
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#define EDMALENH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0D)
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#define EDMADST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0E)
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#define EDMADSTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0E)
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#define EDMADSTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0F)
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#define EDMACS ENC100_TRANSLATE_TO_PIN_ADDR(0x7E10)
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#define EDMACSL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E10)
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#define EDMACSH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E11)
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#define ETXSTAT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E12)
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#define ETXSTATL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E12)
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#define ETXSTATH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E13)
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#define ETXWIRE ENC100_TRANSLATE_TO_PIN_ADDR(0x7E14)
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#define ETXWIREL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E14)
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#define ETXWIREH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E15)
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// SPI all bank registers
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#define EUDAST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E16)
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#define EUDASTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E16)
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#define EUDASTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E17)
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#define EUDAND ENC100_TRANSLATE_TO_PIN_ADDR(0x7E18)
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#define EUDANDL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E18)
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#define EUDANDH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E19)
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#define ESTAT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1A)
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#define ESTATL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1A)
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#define ESTATH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1B)
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#define EIR ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1C)
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#define EIRL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1C)
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#define EIRH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1D)
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#define ECON1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1E)
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#define ECON1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1E)
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#define ECON1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1F)
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// SPI Bank 1 registers -----
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#define EHT1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E20)
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#define EHT1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E20)
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#define EHT1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E21)
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#define EHT2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E22)
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#define EHT2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E22)
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#define EHT2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E23)
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#define EHT3 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E24)
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#define EHT3L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E24)
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#define EHT3H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E25)
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#define EHT4 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E26)
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#define EHT4L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E26)
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#define EHT4H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E27)
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#define EPMM1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E28)
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#define EPMM1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E28)
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#define EPMM1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E29)
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#define EPMM2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2A)
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#define EPMM2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2A)
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#define EPMM2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2B)
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#define EPMM3 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2C)
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#define EPMM3L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2C)
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#define EPMM3H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2D)
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#define EPMM4 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2E)
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||||
#define EPMM4L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2E)
|
||||
#define EPMM4H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2F)
|
||||
#define EPMCS ENC100_TRANSLATE_TO_PIN_ADDR(0x7E30)
|
||||
#define EPMCSL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E30)
|
||||
#define EPMCSH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E31)
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||||
#define EPMO ENC100_TRANSLATE_TO_PIN_ADDR(0x7E32)
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||||
#define EPMOL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E32)
|
||||
#define EPMOH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E33)
|
||||
#define ERXFCON ENC100_TRANSLATE_TO_PIN_ADDR(0x7E34)
|
||||
#define ERXFCONL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E34)
|
||||
#define ERXFCONH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E35)
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||||
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||||
// SPI all bank registers from 0x36 to 0x3F
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||||
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||||
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||||
// SPI Bank 2 registers -----
|
||||
#define MACON1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E40)
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||||
#define MACON1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E40)
|
||||
#define MACON1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E41)
|
||||
#define MACON2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E42)
|
||||
#define MACON2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E42)
|
||||
#define MACON2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E43)
|
||||
#define MABBIPG ENC100_TRANSLATE_TO_PIN_ADDR(0x7E44)
|
||||
#define MABBIPGL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E44)
|
||||
#define MABBIPGH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E45)
|
||||
#define MAIPG ENC100_TRANSLATE_TO_PIN_ADDR(0x7E46)
|
||||
#define MAIPGL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E46)
|
||||
#define MAIPGH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E47)
|
||||
#define MACLCON ENC100_TRANSLATE_TO_PIN_ADDR(0x7E48)
|
||||
#define MACLCONL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E48)
|
||||
#define MACLCONH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E49)
|
||||
#define MAMXFL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4A)
|
||||
#define MAMXFLL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4A)
|
||||
#define MAMXFLH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4B)
|
||||
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4C)
|
||||
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4D)
|
||||
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4E)
|
||||
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4F)
|
||||
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E50)
|
||||
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E51)
|
||||
#define MICMD ENC100_TRANSLATE_TO_PIN_ADDR(0x7E52)
|
||||
#define MICMDL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E52)
|
||||
#define MICMDH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E53)
|
||||
#define MIREGADR ENC100_TRANSLATE_TO_PIN_ADDR(0x7E54)
|
||||
#define MIREGADRL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E54)
|
||||
#define MIREGADRH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E55)
|
||||
|
||||
// SPI all bank registers from 0x56 to 0x5F
|
||||
|
||||
|
||||
// SPI Bank 3 registers -----
|
||||
#define MAADR3 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E60)
|
||||
#define MAADR3L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E60)
|
||||
#define MAADR3H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E61)
|
||||
#define MAADR2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E62)
|
||||
#define MAADR2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E62)
|
||||
#define MAADR2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E63)
|
||||
#define MAADR1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E64)
|
||||
#define MAADR1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E64)
|
||||
#define MAADR1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E65)
|
||||
#define MIWR ENC100_TRANSLATE_TO_PIN_ADDR(0x7E66)
|
||||
#define MIWRL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E66)
|
||||
#define MIWRH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E67)
|
||||
#define MIRD ENC100_TRANSLATE_TO_PIN_ADDR(0x7E68)
|
||||
#define MIRDL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E68)
|
||||
#define MIRDH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E69)
|
||||
#define MISTAT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6A)
|
||||
#define MISTATL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6A)
|
||||
#define MISTATH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6B)
|
||||
#define EPAUS ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6C)
|
||||
#define EPAUSL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6C)
|
||||
#define EPAUSH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6D)
|
||||
#define ECON2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6E)
|
||||
#define ECON2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6E)
|
||||
#define ECON2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6F)
|
||||
#define ERXWM ENC100_TRANSLATE_TO_PIN_ADDR(0x7E70)
|
||||
#define ERXWML ENC100_TRANSLATE_TO_PIN_ADDR(0x7E70)
|
||||
#define ERXWMH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E71)
|
||||
#define EIE ENC100_TRANSLATE_TO_PIN_ADDR(0x7E72)
|
||||
#define EIEL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E72)
|
||||
#define EIEH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E73)
|
||||
#define EIDLED ENC100_TRANSLATE_TO_PIN_ADDR(0x7E74)
|
||||
#define EIDLEDL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E74)
|
||||
#define EIDLEDH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E75)
|
||||
|
||||
// SPI all bank registers from 0x66 to 0x6F
|
||||
|
||||
|
||||
// SPI Non-banked Special Function Registers
|
||||
#define EGPDATA ENC100_TRANSLATE_TO_PIN_ADDR(0x7E80)
|
||||
#define EGPDATAL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E80)
|
||||
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E81)
|
||||
#define ERXDATA ENC100_TRANSLATE_TO_PIN_ADDR(0x7E82)
|
||||
#define ERXDATAL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E82)
|
||||
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E83)
|
||||
#define EUDADATA ENC100_TRANSLATE_TO_PIN_ADDR(0x7E84)
|
||||
#define EUDADATAL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E84)
|
||||
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E85)
|
||||
#define EGPRDPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E86)
|
||||
#define EGPRDPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E86)
|
||||
#define EGPRDPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E87)
|
||||
#define EGPWRPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E88)
|
||||
#define EGPWRPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E88)
|
||||
#define EGPWRPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E89)
|
||||
#define ERXRDPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8A)
|
||||
#define ERXRDPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8A)
|
||||
#define ERXRDPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8B)
|
||||
#define ERXWRPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8C)
|
||||
#define ERXWRPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8C)
|
||||
#define ERXWRPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8D)
|
||||
#define EUDARDPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8E)
|
||||
#define EUDARDPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8E)
|
||||
#define EUDARDPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8F)
|
||||
#define EUDAWRPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E90)
|
||||
#define EUDAWRPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E90)
|
||||
#define EUDAWRPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E91)
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
// ENC424J600/624J600 PHY Register Addresses //
|
||||
////////////////////////////////////////////////////
|
||||
#define PHCON1 0x00
|
||||
#define PHSTAT1 0x01
|
||||
#define PHANA 0x04
|
||||
#define PHANLPA 0x05
|
||||
#define PHANE 0x06
|
||||
#define PHCON2 0x11
|
||||
#define PHSTAT2 0x1B
|
||||
#define PHSTAT3 0x1F
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
// ENC424J600/624J600 register bits //
|
||||
////////////////////////////////////////////////////
|
||||
// ESTAT bits ----------
|
||||
#define ESTAT_INT ((WORD)1<<15)
|
||||
#define ESTAT_FCIDLE ((WORD)1<<14)
|
||||
#define ESTAT_RXBUSY ((WORD)1<<13)
|
||||
#define ESTAT_CLKRDY ((WORD)1<<12)
|
||||
#define ESTAT_RSTDONE ((WORD)1<<11)
|
||||
#define ESTAT_PHYDPX ((WORD)1<<10)
|
||||
#define ESTAT_PHYRDY ((WORD)1<<9)
|
||||
#define ESTAT_PHYLNK ((WORD)1<<8)
|
||||
#define ESTAT_PKTCNT7 (1<<7)
|
||||
#define ESTAT_PKTCNT6 (1<<6)
|
||||
#define ESTAT_PKTCNT5 (1<<5)
|
||||
#define ESTAT_PKTCNT4 (1<<4)
|
||||
#define ESTAT_PKTCNT3 (1<<3)
|
||||
#define ESTAT_PKTCNT2 (1<<2)
|
||||
#define ESTAT_PKTCNT1 (1<<1)
|
||||
#define ESTAT_PKTCNT0 (1)
|
||||
|
||||
// EIR bits ------------
|
||||
#define EIR_CRYPTEN ((WORD)1<<15)
|
||||
#define EIR_MODEXIF ((WORD)1<<14)
|
||||
#define EIR_HASHIF ((WORD)1<<13)
|
||||
#define EIR_AESIF ((WORD)1<<12)
|
||||
#define EIR_LINKIF ((WORD)1<<11)
|
||||
#define EIR_PRDYIF ((WORD)1<<10)
|
||||
#define EIR_r9 ((WORD)1<<9)
|
||||
#define EIR_r8 ((WORD)1<<8)
|
||||
#define EIR_r7 (1<<7)
|
||||
#define EIR_PKTIF (1<<6)
|
||||
#define EIR_DMAIF (1<<5)
|
||||
#define EIR_r4 (1<<4)
|
||||
#define EIR_TXIF (1<<3)
|
||||
#define EIR_TXABTIF (1<<2)
|
||||
#define EIR_RXABTIF (1<<1)
|
||||
#define EIR_PCFULIF (1)
|
||||
|
||||
// ECON1 bits ----------
|
||||
#define ECON1_MODEXST ((WORD)1<<15)
|
||||
#define ECON1_HASHEN ((WORD)1<<14)
|
||||
#define ECON1_HASHOP ((WORD)1<<13)
|
||||
#define ECON1_HASHLST ((WORD)1<<12)
|
||||
#define ECON1_AESST ((WORD)1<<11)
|
||||
#define ECON1_AESOP1 ((WORD)1<<10)
|
||||
#define ECON1_AESOP0 ((WORD)1<<9)
|
||||
#define ECON1_PKTDEC ((WORD)1<<8)
|
||||
#define ECON1_FCOP1 (1<<7)
|
||||
#define ECON1_FCOP0 (1<<6)
|
||||
#define ECON1_DMAST (1<<5)
|
||||
#define ECON1_DMACPY (1<<4)
|
||||
#define ECON1_DMACSSD (1<<3)
|
||||
#define ECON1_DMANOCS (1<<2)
|
||||
#define ECON1_TXRTS (1<<1)
|
||||
#define ECON1_RXEN (1)
|
||||
|
||||
// ETXSTAT bits --------
|
||||
#define ETXSTAT_r12 ((WORD)1<<12)
|
||||
#define ETXSTAT_r11 ((WORD)1<<11)
|
||||
#define ETXSTAT_LATECOL ((WORD)1<<10)
|
||||
#define ETXSTAT_MAXCOL ((WORD)1<<9)
|
||||
#define ETXSTAT_EXDEFER ((WORD)1<<8)
|
||||
#define ETXSTAT_DEFER (1<<7)
|
||||
#define ETXSTAT_r6 (1<<6)
|
||||
#define ETXSTAT_r5 (1<<5)
|
||||
#define ETXSTAT_CRCBAD (1<<4)
|
||||
#define ETXSTAT_COLCNT3 (1<<3)
|
||||
#define ETXSTAT_COLCNT2 (1<<2)
|
||||
#define ETXSTAT_COLCNT1 (1<<1)
|
||||
#define ETXSTAT_COLCNT0 (1)
|
||||
|
||||
// ERXFCON bits --------
|
||||
#define ERXFCON_HTEN ((WORD)1<<15)
|
||||
#define ERXFCON_MPEN ((WORD)1<<14)
|
||||
#define ERXFCON_NOTPM ((WORD)1<<12)
|
||||
#define ERXFCON_PMEN3 ((WORD)1<<11)
|
||||
#define ERXFCON_PMEN2 ((WORD)1<<10)
|
||||
#define ERXFCON_PMEN1 ((WORD)1<<9)
|
||||
#define ERXFCON_PMEN0 ((WORD)1<<8)
|
||||
#define ERXFCON_CRCEEN (1<<7)
|
||||
#define ERXFCON_CRCEN (1<<6)
|
||||
#define ERXFCON_RUNTEEN (1<<5)
|
||||
#define ERXFCON_RUNTEN (1<<4)
|
||||
#define ERXFCON_UCEN (1<<3)
|
||||
#define ERXFCON_NOTMEEN (1<<2)
|
||||
#define ERXFCON_MCEN (1<<1)
|
||||
#define ERXFCON_BCEN (1)
|
||||
|
||||
// MACON1 bits ---------
|
||||
#define MACON1_r15 ((WORD)1<<15)
|
||||
#define MACON1_r14 ((WORD)1<<14)
|
||||
#define MACON1_r11 ((WORD)1<<11)
|
||||
#define MACON1_r10 ((WORD)1<<10)
|
||||
#define MACON1_r9 ((WORD)1<<9)
|
||||
#define MACON1_r8 ((WORD)1<<8)
|
||||
#define MACON1_LOOPBK (1<<4)
|
||||
#define MACON1_r3 (1<<3)
|
||||
#define MACON1_RXPAUS (1<<2)
|
||||
#define MACON1_PASSALL (1<<1)
|
||||
#define MACON1_r0 (1)
|
||||
|
||||
// MACON2 bits ---------
|
||||
#define MACON2_DEFER ((WORD)1<<14)
|
||||
#define MACON2_BPEN ((WORD)1<<13)
|
||||
#define MACON2_NOBKOFF ((WORD)1<<12)
|
||||
#define MACON2_r9 ((WORD)1<<9)
|
||||
#define MACON2_r8 ((WORD)1<<8)
|
||||
#define MACON2_PADCFG2 (1<<7)
|
||||
#define MACON2_PADCFG1 (1<<6)
|
||||
#define MACON2_PADCFG0 (1<<5)
|
||||
#define MACON2_TXCRCEN (1<<4)
|
||||
#define MACON2_PHDREN (1<<3)
|
||||
#define MACON2_HFRMEN (1<<2)
|
||||
#define MACON2_r1 (1<<1)
|
||||
#define MACON2_FULDPX (1)
|
||||
|
||||
// MABBIPG bits --------
|
||||
#define MABBIPG_BBIPG6 (1<<6)
|
||||
#define MABBIPG_BBIPG5 (1<<5)
|
||||
#define MABBIPG_BBIPG4 (1<<4)
|
||||
#define MABBIPG_BBIPG3 (1<<3)
|
||||
#define MABBIPG_BBIPG2 (1<<2)
|
||||
#define MABBIPG_BBIPG1 (1<<1)
|
||||
#define MABBIPG_BBIPG0 (1)
|
||||
|
||||
// MAIPG bits ----------
|
||||
#define MAIPG_r14 ((WORD)1<<14)
|
||||
#define MAIPG_r13 ((WORD)1<<13)
|
||||
#define MAIPG_r12 ((WORD)1<<12)
|
||||
#define MAIPG_r11 ((WORD)1<<11)
|
||||
#define MAIPG_r10 ((WORD)1<<10)
|
||||
#define MAIPG_r9 ((WORD)1<<9)
|
||||
#define MAIPG_r8 ((WORD)1<<8)
|
||||
#define MAIPG_IPG6 (1<<6)
|
||||
#define MAIPG_IPG5 (1<<5)
|
||||
#define MAIPG_IPG4 (1<<4)
|
||||
#define MAIPG_IPG3 (1<<3)
|
||||
#define MAIPG_IPG2 (1<<2)
|
||||
#define MAIPG_IPG1 (1<<1)
|
||||
#define MAIPG_IPG0 (1)
|
||||
|
||||
// MACLCON bits --------
|
||||
#define MACLCON_r13 ((WORD)1<<13)
|
||||
#define MACLCON_r12 ((WORD)1<<12)
|
||||
#define MACLCON_r11 ((WORD)1<<11)
|
||||
#define MACLCON_r10 ((WORD)1<<10)
|
||||
#define MACLCON_r9 ((WORD)1<<9)
|
||||
#define MACLCON_r8 ((WORD)1<<8)
|
||||
#define MACLCON_MAXRET3 (1<<3)
|
||||
#define MACLCON_MAXRET2 (1<<2)
|
||||
#define MACLCON_MAXRET1 (1<<1)
|
||||
#define MACLCON_MAXRET0 (1)
|
||||
|
||||
// MICMD bits ----------
|
||||
#define MICMD_MIISCAN (1<<1)
|
||||
#define MICMD_MIIRD (1)
|
||||
|
||||
// MIREGADR bits -------
|
||||
#define MIREGADR_r12 ((WORD)1<<12)
|
||||
#define MIREGADR_r11 ((WORD)1<<11)
|
||||
#define MIREGADR_r10 ((WORD)1<<10)
|
||||
#define MIREGADR_r9 ((WORD)1<<9)
|
||||
#define MIREGADR_r8 ((WORD)1<<8)
|
||||
#define MIREGADR_PHREG4 (1<<4)
|
||||
#define MIREGADR_PHREG3 (1<<3)
|
||||
#define MIREGADR_PHREG2 (1<<2)
|
||||
#define MIREGADR_PHREG1 (1<<1)
|
||||
#define MIREGADR_PHREG0 (1)
|
||||
|
||||
// MISTAT bits ---------
|
||||
#define MISTAT_r3 (1<<3)
|
||||
#define MISTAT_NVALID (1<<2)
|
||||
#define MISTAT_SCAN (1<<1)
|
||||
#define MISTAT_BUSY (1)
|
||||
|
||||
// ECON2 bits ----------
|
||||
#define ECON2_ETHEN ((WORD)1<<15)
|
||||
#define ECON2_STRCH ((WORD)1<<14)
|
||||
#define ECON2_TXMAC ((WORD)1<<13)
|
||||
#define ECON2_SHA1MD5 ((WORD)1<<12)
|
||||
#define ECON2_COCON3 ((WORD)1<<11)
|
||||
#define ECON2_COCON2 ((WORD)1<<10)
|
||||
#define ECON2_COCON1 ((WORD)1<<9)
|
||||
#define ECON2_COCON0 ((WORD)1<<8)
|
||||
#define ECON2_AUTOFC (1<<7)
|
||||
#define ECON2_TXRST (1<<6)
|
||||
#define ECON2_RXRST (1<<5)
|
||||
#define ECON2_ETHRST (1<<4)
|
||||
#define ECON2_MODLEN1 (1<<3)
|
||||
#define ECON2_MODLEN0 (1<<2)
|
||||
#define ECON2_AESLEN1 (1<<1)
|
||||
#define ECON2_AESLEN0 (1)
|
||||
|
||||
// ERXWM bits ----------
|
||||
#define ERXWM_RXFWM7 ((WORD)1<<15)
|
||||
#define ERXWM_RXFWM6 ((WORD)1<<14)
|
||||
#define ERXWM_RXFWM5 ((WORD)1<<13)
|
||||
#define ERXWM_RXFWM4 ((WORD)1<<12)
|
||||
#define ERXWM_RXFWM3 ((WORD)1<<11)
|
||||
#define ERXWM_RXFWM2 ((WORD)1<<10)
|
||||
#define ERXWM_RXFWM1 ((WORD)1<<9)
|
||||
#define ERXWM_RXFWM0 ((WORD)1<<8)
|
||||
#define ERXWM_RXEWM7 (1<<7)
|
||||
#define ERXWM_RXEWM6 (1<<6)
|
||||
#define ERXWM_RXEWM5 (1<<5)
|
||||
#define ERXWM_RXEWM4 (1<<4)
|
||||
#define ERXWM_RXEWM3 (1<<3)
|
||||
#define ERXWM_RXEWM2 (1<<2)
|
||||
#define ERXWM_RXEWM1 (1<<1)
|
||||
#define ERXWM_RXEWM0 (1)
|
||||
|
||||
// EIE bits ------------
|
||||
#define EIE_INTIE ((WORD)1<<15)
|
||||
#define EIE_MODEXIE ((WORD)1<<14)
|
||||
#define EIE_HASHIE ((WORD)1<<13)
|
||||
#define EIE_AESIE ((WORD)1<<12)
|
||||
#define EIE_LINKIE ((WORD)1<<11)
|
||||
#define EIE_PRDYIE ((WORD)1<<10)
|
||||
#define EIE_r9 ((WORD)1<<9)
|
||||
#define EIE_r8 ((WORD)1<<8)
|
||||
#define EIE_r7 (1<<7)
|
||||
#define EIE_PKTIE (1<<6)
|
||||
#define EIE_DMAIE (1<<5)
|
||||
#define EIE_r4 (1<<4)
|
||||
#define EIE_TXIE (1<<3)
|
||||
#define EIE_TXABTIE (1<<2)
|
||||
#define EIE_RXABTIE (1<<1)
|
||||
#define EIE_PCFULIE (1)
|
||||
|
||||
// EIDLED bits ---------
|
||||
#define EIDLED_LACFG3 ((WORD)1<<15)
|
||||
#define EIDLED_LACFG2 ((WORD)1<<14)
|
||||
#define EIDLED_LACFG1 ((WORD)1<<13)
|
||||
#define EIDLED_LACFG0 ((WORD)1<<12)
|
||||
#define EIDLED_LBCFG3 ((WORD)1<<11)
|
||||
#define EIDLED_LBCFG2 ((WORD)1<<10)
|
||||
#define EIDLED_LBCFG1 ((WORD)1<<9)
|
||||
#define EIDLED_LBCFG0 ((WORD)1<<8)
|
||||
#define EIDLED_DEVID2 (1<<7)
|
||||
#define EIDLED_DEVID1 (1<<6)
|
||||
#define EIDLED_DEVID0 (1<<5)
|
||||
#define EIDLED_REVID4 (1<<4)
|
||||
#define EIDLED_REVID3 (1<<3)
|
||||
#define EIDLED_REVID2 (1<<2)
|
||||
#define EIDLED_REVID1 (1<<1)
|
||||
#define EIDLED_REVID0 (1)
|
||||
|
||||
// PHCON1 bits ---------
|
||||
#define PHCON1_PRST ((WORD)1<<15)
|
||||
#define PHCON1_PLOOPBK ((WORD)1<<14)
|
||||
#define PHCON1_SPD100 ((WORD)1<<13)
|
||||
#define PHCON1_ANEN ((WORD)1<<12)
|
||||
#define PHCON1_PSLEEP ((WORD)1<<11)
|
||||
#define PHCON1_r10 ((WORD)1<<10)
|
||||
#define PHCON1_RENEG ((WORD)1<<9)
|
||||
#define PHCON1_PFULDPX ((WORD)1<<8)
|
||||
#define PHCON1_r7 (1<<7)
|
||||
#define PHCON1_r6 (1<<6)
|
||||
#define PHCON1_r5 (1<<5)
|
||||
#define PHCON1_r4 (1<<4)
|
||||
#define PHCON1_r3 (1<<3)
|
||||
#define PHCON1_r2 (1<<2)
|
||||
#define PHCON1_r1 (1<<1)
|
||||
#define PHCON1_r0 (1)
|
||||
|
||||
// PHSTAT1 bits --------
|
||||
#define PHSTAT1_r15 ((WORD)1<<15)
|
||||
#define PHSTAT1_FULL100 ((WORD)1<<14)
|
||||
#define PHSTAT1_HALF100 ((WORD)1<<13)
|
||||
#define PHSTAT1_FULL10 ((WORD)1<<12)
|
||||
#define PHSTAT1_HALF10 ((WORD)1<<11)
|
||||
#define PHSTAT1_r10 ((WORD)1<<10)
|
||||
#define PHSTAT1_r9 ((WORD)1<<9)
|
||||
#define PHSTAT1_r8 ((WORD)1<<8)
|
||||
#define PHSTAT1_r7 (1<<7)
|
||||
#define PHSTAT1_r6 (1<<6)
|
||||
#define PHSTAT1_ANDONE (1<<5)
|
||||
#define PHSTAT1_LRFAULT (1<<4)
|
||||
#define PHSTAT1_ANABLE (1<<3)
|
||||
#define PHSTAT1_LLSTAT (1<<2)
|
||||
#define PHSTAT1_r1 (1<<1)
|
||||
#define PHSTAT1_EXTREGS (1)
|
||||
|
||||
// PHANA bits ----------
|
||||
#define PHANA_ADNP ((WORD)1<<15)
|
||||
#define PHANA_r14 ((WORD)1<<14)
|
||||
#define PHANA_ADFAULT ((WORD)1<<13)
|
||||
#define PHANA_r12 ((WORD)1<<12)
|
||||
#define PHANA_ADPAUS1 ((WORD)1<<11)
|
||||
#define PHANA_ADPAUS0 ((WORD)1<<10)
|
||||
#define PHANA_r9 ((WORD)1<<9)
|
||||
#define PHANA_AD100FD ((WORD)1<<8)
|
||||
#define PHANA_AD100 (1<<7)
|
||||
#define PHANA_AD10FD (1<<6)
|
||||
#define PHANA_AD10 (1<<5)
|
||||
#define PHANA_ADIEEE4 (1<<4)
|
||||
#define PHANA_ADIEEE3 (1<<3)
|
||||
#define PHANA_ADIEEE2 (1<<2)
|
||||
#define PHANA_ADIEEE1 (1<<1)
|
||||
#define PHANA_ADIEEE0 (1)
|
||||
|
||||
// PHANLPA bits --------
|
||||
#define PHANLPA_LPNP ((WORD)1<<15)
|
||||
#define PHANLPA_LPACK ((WORD)1<<14)
|
||||
#define PHANLPA_LPFAULT ((WORD)1<<13)
|
||||
#define PHANLPA_r12 ((WORD)1<<12)
|
||||
#define PHANLPA_LPPAUS1 ((WORD)1<<11)
|
||||
#define PHANLPA_LPPAUS0 ((WORD)1<<10)
|
||||
#define PHANLPA_LP100T4 ((WORD)1<<9)
|
||||
#define PHANLPA_LP100FD ((WORD)1<<8)
|
||||
#define PHANLPA_LP100 (1<<7)
|
||||
#define PHANLPA_LP10FD (1<<6)
|
||||
#define PHANLPA_LP10 (1<<5)
|
||||
#define PHANLPA_LPIEEE4 (1<<4)
|
||||
#define PHANLPA_LPIEEE3 (1<<3)
|
||||
#define PHANLPA_LPIEEE2 (1<<2)
|
||||
#define PHANLPA_LPIEEE1 (1<<1)
|
||||
#define PHANLPA_LPIEEE0 (1)
|
||||
|
||||
// PHANE bits ----------
|
||||
#define PHANE_r15 ((WORD)1<<15)
|
||||
#define PHANE_r14 ((WORD)1<<14)
|
||||
#define PHANE_r13 ((WORD)1<<13)
|
||||
#define PHANE_r12 ((WORD)1<<12)
|
||||
#define PHANE_r11 ((WORD)1<<11)
|
||||
#define PHANE_r10 ((WORD)1<<10)
|
||||
#define PHANE_r9 ((WORD)1<<9)
|
||||
#define PHANE_r8 ((WORD)1<<8)
|
||||
#define PHANE_r7 (1<<7)
|
||||
#define PHANE_r6 (1<<6)
|
||||
#define PHANE_r5 (1<<5)
|
||||
#define PHANE_PDFLT (1<<4)
|
||||
#define PHANE_r3 (1<<3)
|
||||
#define PHANE_r2 (1<<2)
|
||||
#define PHANE_LPARCD (1<<1)
|
||||
#define PHANA_LPANABL (1)
|
||||
|
||||
// PHCON2 bits ---------
|
||||
#define PHCON2_r15 ((WORD)1<<15)
|
||||
#define PHCON2_r14 ((WORD)1<<14)
|
||||
#define PHCON2_EDPWRDN ((WORD)1<<13)
|
||||
#define PHCON2_r12 ((WORD)1<<12)
|
||||
#define PHCON2_EDTHRES ((WORD)1<<11)
|
||||
#define PHCON2_r10 ((WORD)1<<10)
|
||||
#define PHCON2_r9 ((WORD)1<<9)
|
||||
#define PHCON2_r8 ((WORD)1<<8)
|
||||
#define PHCON2_r7 (1<<7)
|
||||
#define PHCON2_r6 (1<<6)
|
||||
#define PHCON2_r5 (1<<5)
|
||||
#define PHCON2_r4 (1<<4)
|
||||
#define PHCON2_r3 (1<<3)
|
||||
#define PHCON2_FRCLNK (1<<2)
|
||||
#define PHCON2_EDSTAT (1<<1)
|
||||
#define PHCON2_r0 (1)
|
||||
|
||||
// PHSTAT2 bits ---------
|
||||
#define PHSTAT2_r15 ((WORD)1<<15)
|
||||
#define PHSTAT2_r14 ((WORD)1<<14)
|
||||
#define PHSTAT2_r13 ((WORD)1<<13)
|
||||
#define PHSTAT2_r12 ((WORD)1<<12)
|
||||
#define PHSTAT2_r11 ((WORD)1<<11)
|
||||
#define PHSTAT2_r10 ((WORD)1<<10)
|
||||
#define PHSTAT2_r9 ((WORD)1<<9)
|
||||
#define PHSTAT2_r8 ((WORD)1<<8)
|
||||
#define PHSTAT2_r7 (1<<7)
|
||||
#define PHSTAT2_r6 (1<<6)
|
||||
#define PHSTAT2_r5 (1<<5)
|
||||
#define PHSTAT2_PLRITY (1<<4)
|
||||
#define PHSTAT2_r3 (1<<3)
|
||||
#define PHSTAT2_r2 (1<<2)
|
||||
#define PHSTAT2_r1 (1<<1)
|
||||
#define PHSTAT2_r0 (1)
|
||||
|
||||
// PHSTAT3 bits --------
|
||||
#define PHSTAT3_r15 ((WORD)1<<15)
|
||||
#define PHSTAT3_r14 ((WORD)1<<14)
|
||||
#define PHSTAT3_r13 ((WORD)1<<13)
|
||||
#define PHSTAT3_r12 ((WORD)1<<12)
|
||||
#define PHSTAT3_r11 ((WORD)1<<11)
|
||||
#define PHSTAT3_r10 ((WORD)1<<10)
|
||||
#define PHSTAT3_r9 ((WORD)1<<9)
|
||||
#define PHSTAT3_r8 ((WORD)1<<8)
|
||||
#define PHSTAT3_r7 (1<<7)
|
||||
#define PHSTAT3_r6 (1<<6)
|
||||
#define PHSTAT3_r5 (1<<5)
|
||||
#define PHSTAT3_SPDDPX2 (1<<4)
|
||||
#define PHSTAT3_SPDDPX1 (1<<3)
|
||||
#define PHSTAT3_SPDDPX0 (1<<2)
|
||||
#define PHSTAT3_r1 (1<<1)
|
||||
#define PHSTAT3_r0 (1)
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,281 @@
|
||||
/*********************************************************************
|
||||
*
|
||||
* Generic Type Definitions
|
||||
*
|
||||
*********************************************************************
|
||||
* FileName: GenericTypeDefs.h
|
||||
* Dependencies: None
|
||||
* Processor: PIC18, PIC24, dsPIC, PIC32
|
||||
* Compiler: Microchip C18, C30, C32
|
||||
* Company: Microchip Technology, Inc.
|
||||
*
|
||||
* Software License Agreement
|
||||
*
|
||||
* The software supplied herewith by Microchip Technology Incorporated
|
||||
* (the "Company") is intended and supplied to you, the Company's
|
||||
* customer, for use solely and exclusively with products manufactured
|
||||
* by the Company.
|
||||
*
|
||||
* The software is owned by the Company and/or its supplier, and is
|
||||
* protected under applicable copyright laws. All rights are reserved.
|
||||
* Any use in violation of the foregoing restrictions may subject the
|
||||
* user to criminal sanctions under applicable laws, as well as to
|
||||
* civil liability for the breach of the terms and conditions of this
|
||||
* license.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
|
||||
* TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
||||
* PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,
|
||||
* IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*********************************************************************
|
||||
* File Description:
|
||||
*
|
||||
* Change History:
|
||||
* Rev Date Description
|
||||
* 1.1 09/11/06 Add base signed types
|
||||
* 1.2 02/28/07 Add QWORD, LONGLONG, QWORD_VAL
|
||||
* 1.3 02/06/08 Add def's for PIC32
|
||||
* 1.4 08/08/08 Remove LSB/MSB Macros, adopted by Peripheral lib
|
||||
* 1.5 08/14/08 Simplify file header
|
||||
********************************************************************/
|
||||
|
||||
#ifndef __GENERIC_TYPE_DEFS_H_
|
||||
#define __GENERIC_TYPE_DEFS_H_
|
||||
|
||||
typedef enum _BOOL { FALSE = 0, TRUE } BOOL; // Undefined size
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0//((void *)0)
|
||||
#endif
|
||||
|
||||
#define PUBLIC // Function attributes
|
||||
#define PROTECTED
|
||||
#define PRIVATE static
|
||||
|
||||
typedef unsigned char BYTE; // 8-bit unsigned
|
||||
typedef unsigned short int WORD; // 16-bit unsigned
|
||||
typedef unsigned long DWORD; // 32-bit unsigned
|
||||
typedef unsigned long long QWORD; // 64-bit unsigned
|
||||
typedef signed char CHAR; // 8-bit signed
|
||||
typedef signed short int SHORT; // 16-bit signed
|
||||
typedef signed long LONG; // 32-bit signed
|
||||
typedef signed long long LONGLONG; // 64-bit signed
|
||||
|
||||
/* Alternate definitions */
|
||||
typedef void VOID;
|
||||
|
||||
typedef char CHAR8;
|
||||
typedef unsigned char UCHAR8;
|
||||
|
||||
/* Processor & Compiler independent, size specific definitions */
|
||||
// To Do: We need to verify the sizes on each compiler. These
|
||||
// may be compiler specific, we should either move them
|
||||
// to "compiler.h" or #ifdef them for compiler type.
|
||||
typedef signed int INT;
|
||||
typedef signed char INT8;
|
||||
typedef signed short int INT16;
|
||||
typedef signed long int INT32;
|
||||
typedef signed long long INT64;
|
||||
|
||||
typedef unsigned int UINT;
|
||||
typedef unsigned char UINT8;
|
||||
typedef unsigned short int UINT16;
|
||||
typedef unsigned long int UINT32; // other name for 32-bit integer
|
||||
typedef unsigned long long UINT64;
|
||||
|
||||
typedef union _BYTE_VAL
|
||||
{
|
||||
BYTE Val;
|
||||
struct
|
||||
{
|
||||
unsigned char b0:1;
|
||||
unsigned char b1:1;
|
||||
unsigned char b2:1;
|
||||
unsigned char b3:1;
|
||||
unsigned char b4:1;
|
||||
unsigned char b5:1;
|
||||
unsigned char b6:1;
|
||||
unsigned char b7:1;
|
||||
} bits;
|
||||
} BYTE_VAL, BYTE_BITS;
|
||||
|
||||
typedef union _WORD_VAL
|
||||
{
|
||||
WORD Val;
|
||||
BYTE v[2];
|
||||
struct
|
||||
{
|
||||
BYTE LB;
|
||||
BYTE HB;
|
||||
} byte;
|
||||
struct
|
||||
{
|
||||
unsigned char b0:1;
|
||||
unsigned char b1:1;
|
||||
unsigned char b2:1;
|
||||
unsigned char b3:1;
|
||||
unsigned char b4:1;
|
||||
unsigned char b5:1;
|
||||
unsigned char b6:1;
|
||||
unsigned char b7:1;
|
||||
unsigned char b8:1;
|
||||
unsigned char b9:1;
|
||||
unsigned char b10:1;
|
||||
unsigned char b11:1;
|
||||
unsigned char b12:1;
|
||||
unsigned char b13:1;
|
||||
unsigned char b14:1;
|
||||
unsigned char b15:1;
|
||||
} bits;
|
||||
} WORD_VAL, WORD_BITS;
|
||||
|
||||
typedef union _DWORD_VAL
|
||||
{
|
||||
DWORD Val;
|
||||
WORD w[2];
|
||||
BYTE v[4];
|
||||
struct
|
||||
{
|
||||
WORD LW;
|
||||
WORD HW;
|
||||
} word;
|
||||
struct
|
||||
{
|
||||
BYTE LB;
|
||||
BYTE HB;
|
||||
BYTE UB;
|
||||
BYTE MB;
|
||||
} byte;
|
||||
struct
|
||||
{
|
||||
WORD_VAL low;
|
||||
WORD_VAL high;
|
||||
}wordUnion;
|
||||
struct
|
||||
{
|
||||
unsigned char b0:1;
|
||||
unsigned char b1:1;
|
||||
unsigned char b2:1;
|
||||
unsigned char b3:1;
|
||||
unsigned char b4:1;
|
||||
unsigned char b5:1;
|
||||
unsigned char b6:1;
|
||||
unsigned char b7:1;
|
||||
unsigned char b8:1;
|
||||
unsigned char b9:1;
|
||||
unsigned char b10:1;
|
||||
unsigned char b11:1;
|
||||
unsigned char b12:1;
|
||||
unsigned char b13:1;
|
||||
unsigned char b14:1;
|
||||
unsigned char b15:1;
|
||||
unsigned char b16:1;
|
||||
unsigned char b17:1;
|
||||
unsigned char b18:1;
|
||||
unsigned char b19:1;
|
||||
unsigned char b20:1;
|
||||
unsigned char b21:1;
|
||||
unsigned char b22:1;
|
||||
unsigned char b23:1;
|
||||
unsigned char b24:1;
|
||||
unsigned char b25:1;
|
||||
unsigned char b26:1;
|
||||
unsigned char b27:1;
|
||||
unsigned char b28:1;
|
||||
unsigned char b29:1;
|
||||
unsigned char b30:1;
|
||||
unsigned char b31:1;
|
||||
} bits;
|
||||
} DWORD_VAL;
|
||||
|
||||
typedef union _QWORD_VAL
|
||||
{
|
||||
QWORD Val;
|
||||
DWORD d[2];
|
||||
WORD w[4];
|
||||
BYTE v[8];
|
||||
struct
|
||||
{
|
||||
DWORD LD;
|
||||
DWORD HD;
|
||||
} dword;
|
||||
struct
|
||||
{
|
||||
WORD LW;
|
||||
WORD HW;
|
||||
WORD UW;
|
||||
WORD MW;
|
||||
} word;
|
||||
struct
|
||||
{
|
||||
unsigned char b0:1;
|
||||
unsigned char b1:1;
|
||||
unsigned char b2:1;
|
||||
unsigned char b3:1;
|
||||
unsigned char b4:1;
|
||||
unsigned char b5:1;
|
||||
unsigned char b6:1;
|
||||
unsigned char b7:1;
|
||||
unsigned char b8:1;
|
||||
unsigned char b9:1;
|
||||
unsigned char b10:1;
|
||||
unsigned char b11:1;
|
||||
unsigned char b12:1;
|
||||
unsigned char b13:1;
|
||||
unsigned char b14:1;
|
||||
unsigned char b15:1;
|
||||
unsigned char b16:1;
|
||||
unsigned char b17:1;
|
||||
unsigned char b18:1;
|
||||
unsigned char b19:1;
|
||||
unsigned char b20:1;
|
||||
unsigned char b21:1;
|
||||
unsigned char b22:1;
|
||||
unsigned char b23:1;
|
||||
unsigned char b24:1;
|
||||
unsigned char b25:1;
|
||||
unsigned char b26:1;
|
||||
unsigned char b27:1;
|
||||
unsigned char b28:1;
|
||||
unsigned char b29:1;
|
||||
unsigned char b30:1;
|
||||
unsigned char b31:1;
|
||||
unsigned char b32:1;
|
||||
unsigned char b33:1;
|
||||
unsigned char b34:1;
|
||||
unsigned char b35:1;
|
||||
unsigned char b36:1;
|
||||
unsigned char b37:1;
|
||||
unsigned char b38:1;
|
||||
unsigned char b39:1;
|
||||
unsigned char b40:1;
|
||||
unsigned char b41:1;
|
||||
unsigned char b42:1;
|
||||
unsigned char b43:1;
|
||||
unsigned char b44:1;
|
||||
unsigned char b45:1;
|
||||
unsigned char b46:1;
|
||||
unsigned char b47:1;
|
||||
unsigned char b48:1;
|
||||
unsigned char b49:1;
|
||||
unsigned char b50:1;
|
||||
unsigned char b51:1;
|
||||
unsigned char b52:1;
|
||||
unsigned char b53:1;
|
||||
unsigned char b54:1;
|
||||
unsigned char b55:1;
|
||||
unsigned char b56:1;
|
||||
unsigned char b57:1;
|
||||
unsigned char b58:1;
|
||||
unsigned char b59:1;
|
||||
unsigned char b60:1;
|
||||
unsigned char b61:1;
|
||||
unsigned char b62:1;
|
||||
unsigned char b63:1;
|
||||
} bits;
|
||||
} QWORD_VAL;
|
||||
|
||||
#endif //__GENERIC_TYPE_DEFS_H_
|
||||
@@ -0,0 +1,227 @@
|
||||
/*********************************************************************
|
||||
*
|
||||
* Hardware specific definitions for PIC32 Starter Kit (GP or USB) +
|
||||
* PIC32 I/O Expansion Board + Ethernet PICtail Plus (ENC28J60) or
|
||||
* Fast 100Mbps Ethernet PICtail Plus (ENC624J600)
|
||||
*
|
||||
*********************************************************************
|
||||
* FileName: HardwareProfile.h
|
||||
* Dependencies: None
|
||||
* Processor: PIC32
|
||||
* Compiler: Microchip C32 v1.05 or higher
|
||||
* Company: Microchip Technology, Inc.
|
||||
*
|
||||
* Software License Agreement
|
||||
*
|
||||
* Copyright (C) 2002-2009 Microchip Technology Inc. All rights
|
||||
* reserved.
|
||||
*
|
||||
* Microchip licenses to you the right to use, modify, copy, and
|
||||
* distribute:
|
||||
* (i) the Software when embedded on a Microchip microcontroller or
|
||||
* digital signal controller product ("Device") which is
|
||||
* integrated into Licensee's product; or
|
||||
* (ii) ONLY the Software driver source files ENC28J60.c, ENC28J60.h,
|
||||
* ENCX24J600.c and ENCX24J600.h ported to a non-Microchip device
|
||||
* used in conjunction with a Microchip ethernet controller for
|
||||
* the sole purpose of interfacing with the ethernet controller.
|
||||
*
|
||||
* You should refer to the license agreement accompanying this
|
||||
* Software for additional information regarding your rights and
|
||||
* obligations.
|
||||
*
|
||||
* THE SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT
|
||||
* WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT
|
||||
* LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
* MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
|
||||
* BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE
|
||||
* THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER
|
||||
* SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT
|
||||
* (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE.
|
||||
*
|
||||
*
|
||||
* Author Date Comment
|
||||
*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
* Aseem swalah 02/03/09 Copied from the TCPIP Demo App
|
||||
********************************************************************/
|
||||
#ifndef __HARDWARE_PROFILE_H
|
||||
#define __HARDWARE_PROFILE_H
|
||||
|
||||
#include "GenericTypeDefs.h"
|
||||
#include "Compiler.h"
|
||||
|
||||
|
||||
// Set configuration fuses (but only once)
|
||||
#if defined(THIS_IS_STACK_APPLICATION)
|
||||
#pragma config FPLLODIV = DIV_1, FPLLMUL = MUL_20, FPLLIDIV = DIV_2, FWDTEN = OFF, FPBDIV = DIV_1, POSCMOD = XT, FNOSC = PRIPLL, CP = OFF
|
||||
#endif
|
||||
|
||||
// Clock frequency value.
|
||||
// This value is used to calculate Tick Counter value
|
||||
#define GetSystemClock() (80000000ul) // Hz
|
||||
#define GetInstructionClock() (GetSystemClock()/1)
|
||||
#define GetPeripheralClock() (GetInstructionClock()/1) // Set your divider according to your Peripheral Bus Frequency configuration fuse setting
|
||||
|
||||
|
||||
// Specify which SPI to use for the ENC624J600.
|
||||
#define ENC_IN_SPI2
|
||||
|
||||
|
||||
// Hardware mappings
|
||||
#define LED0_TRIS (TRISDbits.TRISD0) // Ref LED1
|
||||
#define LED0_IO (LATDbits.LATD0)
|
||||
#define LED1_TRIS (TRISDbits.TRISD1) // Ref LED2
|
||||
#define LED1_IO (LATDbits.LATD1)
|
||||
#define LED2_TRIS (TRISDbits.TRISD2) // Ref LED3
|
||||
#define LED2_IO (LATDbits.LATD2)
|
||||
#define LED3_TRIS (LED2_TRIS) // No such LED
|
||||
#define LED3_IO (LATDbits.LATD6)
|
||||
#define LED4_TRIS (LED2_TRIS) // No such LED
|
||||
#define LED4_IO (LATDbits.LATD6)
|
||||
#define LED5_TRIS (LED2_TRIS) // No such LED
|
||||
#define LED5_IO (LATDbits.LATD6)
|
||||
#define LED6_TRIS (LED2_TRIS) // No such LED
|
||||
#define LED6_IO (LATDbits.LATD6)
|
||||
#define LED7_TRIS (LED2_TRIS) // No such LED
|
||||
#define LED7_IO (LATDbits.LATD6)
|
||||
|
||||
#define LED_GET() ((BYTE)LATD & 0x07)
|
||||
#define LED_PUT(a) do{LATD = (LATD & 0xFFF8) | ((a)&0x07);}while(0)
|
||||
|
||||
#define BUTTON0_TRIS (TRISDbits.TRISD6) // Ref SW1
|
||||
#define BUTTON0_IO (PORTDbits.RD6)
|
||||
#define BUTTON1_TRIS (TRISDbits.TRISD7) // Ref SW2
|
||||
#define BUTTON1_IO (PORTDbits.RD7)
|
||||
#define BUTTON2_TRIS (TRISDbits.TRISD13) // Ref SW3
|
||||
#define BUTTON2_IO (PORTDbits.RD13)
|
||||
#define BUTTON3_TRIS (TRISDbits.TRISD13) // No BUTTON3 on this board
|
||||
#define BUTTON3_IO (1)
|
||||
|
||||
|
||||
|
||||
// ENC624J600 Interface Configuration
|
||||
// Comment out ENC100_INTERFACE_MODE if you don't have an ENC624J600 or
|
||||
// ENC424J600. Otherwise, choose the correct setting for the interface you
|
||||
// are using. Legal values are:
|
||||
// - Commented out: No ENC424J600/624J600 present or used. All other
|
||||
// ENC100_* macros are ignored.
|
||||
// - 0: SPI mode using CS, SCK, SI, and SO pins
|
||||
// - 1: 8-bit demultiplexed PSP Mode 1 with RD and WR pins
|
||||
// - 2: 8-bit demultiplexed PSP Mode 2 with R/Wbar and EN pins
|
||||
// - 3: 16-bit demultiplexed PSP Mode 3 with RD, WRL, and WRH pins
|
||||
// - 4: 16-bit demultiplexed PSP Mode 4 with R/Wbar, B0SEL, and B1SEL pins
|
||||
// - 5: 8-bit multiplexed PSP Mode 5 with RD and WR pins
|
||||
// - 6: 8-bit multiplexed PSP Mode 6 with R/Wbar and EN pins
|
||||
// - 9: 16-bit multiplexed PSP Mode 9 with AL, RD, WRL, and WRH pins
|
||||
// - 10: 16-bit multiplexed PSP Mode 10 with AL, R/Wbar, B0SEL, and B1SEL
|
||||
// pins
|
||||
#define ENC100_INTERFACE_MODE 3
|
||||
|
||||
// If using a parallel interface, direct RAM addressing can be used (if all
|
||||
// addresses wires are connected), or a reduced number of pins can be used
|
||||
// for indirect addressing. If using an SPI interface or PSP Mode 9 or 10
|
||||
// (multiplexed 16-bit modes), which require all address lines to always be
|
||||
// connected, then this option is ignored. Comment out or uncomment this
|
||||
// macro to match your hardware connections.
|
||||
#define ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING
|
||||
|
||||
// ENC424J600/624J600 parallel indirect address remapping macro function.
|
||||
// This section translates SFR and RAM addresses presented to the
|
||||
// ReadMemory() and WriteMemory() APIs in ENCX24J600.c to the actual
|
||||
// addresses that must be presented on the parallel interface. This macro
|
||||
// must be modified to match your hardware if you are using an indirect PSP
|
||||
// addressing mode (ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING is defined) and
|
||||
// have some of your address lines tied off to Vdd. If you are using the
|
||||
// SPI interface, then this section can be ignored or deleted.
|
||||
#if (ENC100_INTERFACE_MODE == 1) || (ENC100_INTERFACE_MODE == 2) || (ENC100_INTERFACE_MODE == 5) || (ENC100_INTERFACE_MODE == 6) // 8-bit PSP
|
||||
#define ENC100_TRANSLATE_TO_PIN_ADDR(a) ((((a)&0x0100)<<6) | ((a)&0x00FF))
|
||||
#elif (ENC100_INTERFACE_MODE == 3) || (ENC100_INTERFACE_MODE == 4) // 16-bit PSP
|
||||
#define ENC100_TRANSLATE_TO_PIN_ADDR(a) (a)
|
||||
#endif
|
||||
|
||||
// Auto-crossover pins on Fast 100Mbps Ethernet PICtail/PICtail Plus. If
|
||||
// your circuit doesn't have such a feature, delete these two defines.
|
||||
#define ENC100_MDIX_TRIS (TRISBbits.TRISB3)
|
||||
#define ENC100_MDIX_IO (LATBbits.LATB3)
|
||||
|
||||
// ENC624J600 I/O control and status pins
|
||||
// If a pin is not required for your selected ENC100_INTERFACE_MODE
|
||||
// interface selection (ex: WRH/B1SEL for PSP modes 1, 2, 5, and 6), then
|
||||
// you can ignore, delete, or put anything for the pin definition. Also,
|
||||
// the INT and POR pins are entirely optional. If not connected, comment
|
||||
// them out.
|
||||
#define ENC100_INT_TRIS (TRISEbits.TRISE9) // INT signal is optional and currently unused in the Microchip TCP/IP Stack. Leave this pin disconnected and comment out this pin definition if you don't want it.
|
||||
#define ENC100_INT_IO (PORTEbits.RE9)
|
||||
#if (ENC100_INTERFACE_MODE >= 1) // Parallel mode
|
||||
// PSP control signal pinout
|
||||
#define ENC100_CS_TRIS (TRISAbits.TRISA5) // CS is optional in PSP mode. If you are not sharing the parallel bus with another device, tie CS to Vdd and comment out this pin definition.
|
||||
#define ENC100_CS_IO (LATAbits.LATA5)
|
||||
#define ENC100_POR_TRIS (TRISCbits.TRISC1) // POR signal is optional. If your application doesn't have a power disconnect feature, comment out this pin definition.
|
||||
#define ENC100_POR_IO (LATCbits.LATC1)
|
||||
#define ENC100_SO_WR_B0SEL_EN_TRIS (TRISDbits.TRISD4)
|
||||
#define ENC100_SO_WR_B0SEL_EN_IO (LATDbits.LATD4)
|
||||
#define ENC100_SI_RD_RW_TRIS (TRISDbits.TRISD5)
|
||||
#define ENC100_SI_RD_RW_IO (LATDbits.LATD5)
|
||||
#define ENC100_SCK_AL_TRIS (TRISBbits.TRISB15)
|
||||
#define ENC100_SCK_AL_IO (LATBbits.LATB15)
|
||||
#else
|
||||
// SPI pinout
|
||||
#if defined ENC_IN_SPI1
|
||||
#define ENC100_CS_TRIS (TRISDbits.TRISD14) // CS is mandatory when using the SPI interface
|
||||
#define ENC100_CS_IO (LATDbits.LATD14)
|
||||
#define ENC100_POR_TRIS (TRISDbits.TRISD15) // POR signal is optional. If your application doesn't have a power disconnect feature, comment out this pin definition.
|
||||
#define ENC100_POR_IO (LATDbits.LATD15)
|
||||
#define ENC100_SO_WR_B0SEL_EN_TRIS (TRISFbits.TRISF7) // SO is ENCX24J600 Serial Out, which needs to connect to the PIC SDI pin for SPI mode
|
||||
#define ENC100_SO_WR_B0SEL_EN_IO (PORTFbits.RF7)
|
||||
#define ENC100_SI_RD_RW_TRIS (TRISFbits.TRISF8) // SI is ENCX24J600 Serial In, which needs to connect to the PIC SDO pin for SPI mode
|
||||
#define ENC100_SI_RD_RW_IO (LATFbits.LATF8)
|
||||
#define ENC100_SCK_AL_TRIS (TRISFbits.TRISF6)
|
||||
#elif defined ENC_IN_SPI2
|
||||
#define ENC100_CS_TRIS (TRISFbits.TRISF12)
|
||||
#define ENC100_CS_IO (LATFbits.LATF12)
|
||||
#define ENC100_POR_TRIS (TRISFbits.TRISF13)
|
||||
#define ENC100_POR_IO (LATFbits.LATF13)
|
||||
#define ENC100_SO_WR_B0SEL_EN_TRIS (TRISGbits.TRISG7) // NOTE: SO is ENC624J600 Serial Out, which needs to connect to the PIC SDI pin for SPI mode
|
||||
#define ENC100_SO_WR_B0SEL_EN_IO (PORTGbits.RG7)
|
||||
#define ENC100_SI_RD_RW_TRIS (TRISGbits.TRISG8) // NOTE: SI is ENC624J600 Serial In, which needs to connect to the PIC SDO pin for SPI mode
|
||||
#define ENC100_SI_RD_RW_IO (LATGbits.LATG8)
|
||||
#define ENC100_SCK_AL_TRIS (TRISGbits.TRISG6)
|
||||
#define ENC100_SCK_AL_IO (PORTGbits.RG6) // NOTE: This must be the PORT, not the LATch like it is for the PSP interface.
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
// ENC624J600 SPI SFR register selection (controls which SPI peripheral to
|
||||
// use on PICs with multiple SPI peripherals). If a parallel interface is
|
||||
// used (ENC100_INTERFACE_MODE is >= 1), then the SPI is not used and this
|
||||
// section can be ignored or deleted.
|
||||
#if defined ENC_IN_SPI1
|
||||
#define ENC100_ISR_ENABLE (IEC0bits.INT2IE)
|
||||
#define ENC100_ISR_FLAG (IFS0bits.INT2IF)
|
||||
#define ENC100_ISR_POLARITY (INTCONbits.INT2EP)
|
||||
#define ENC100_ISR_PRIORITY (IPC2bits.INT2IP)
|
||||
#define ENC100_SPI_ENABLE (ENC100_SPICON1bits.ON)
|
||||
#define ENC100_SPI_IF (IFS0bits.SPI1RXIF)
|
||||
#define ENC100_SSPBUF (SPI1BUF)
|
||||
#define ENC100_SPICON1 (SPI1CON)
|
||||
#define ENC100_SPISTATbits (SPI1STATbits)
|
||||
#define ENC100_SPICON1bits (SPI1CONbits)
|
||||
#define ENC100_SPIBRG (SPI1BRG)
|
||||
#elif defined ENC_IN_SPI2
|
||||
#define ENC100_ISR_ENABLE (IEC0bits.INT4IE)
|
||||
#define ENC100_ISR_FLAG (IFS0bits.INT4IF)
|
||||
#define ENC100_ISR_POLARITY (INTCONbits.INT4EP)
|
||||
#define ENC100_ISR_PRIORITY (IPC2bits.INT4IP)
|
||||
#define ENC100_SPI_ENABLE (ENC100_SPICON1bits.ON)
|
||||
#define ENC100_SPI_IF (IFS1bits.SPI2RXIF)
|
||||
#define ENC100_SSPBUF (SPI2BUF)
|
||||
#define ENC100_SPICON1 (SPI2CON)
|
||||
#define ENC100_SPISTATbits (SPI2STATbits)
|
||||
#define ENC100_SPICON1bits (SPI2CONbits)
|
||||
#define ENC100_SPIBRG (SPI2BRG)
|
||||
#endif
|
||||
|
||||
#endif //__HARDWARE_PROFILE_H
|
||||
Binary file not shown.
@@ -0,0 +1,6 @@
|
||||
|
||||
/* MACHINE GENERATED */
|
||||
|
||||
|
||||
/* InitLAN.c */
|
||||
|
||||
@@ -0,0 +1,161 @@
|
||||
#include "InitLAN.h"
|
||||
|
||||
|
||||
unsigned long hex2int(char *a)
|
||||
{
|
||||
int i,len=0;
|
||||
unsigned long val = 0;
|
||||
|
||||
while(a[len])
|
||||
len++;
|
||||
|
||||
for(i=0;i<len;i++)
|
||||
if(a[i] <= 57)
|
||||
val += (a[i]-48)*(1<<(4*(len-1-i)));
|
||||
else
|
||||
val += (a[i]-55)*(1<<(4*(len-1-i)));
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
BYTE delayCIA(){ //one CIA acces: 1.4 micro sec
|
||||
return (CIA_TST);
|
||||
}
|
||||
|
||||
WORD delayShort(){
|
||||
return (CHP_TST);
|
||||
}
|
||||
|
||||
|
||||
|
||||
int SoftReset(APTR *BaseAddress){
|
||||
int i;
|
||||
WORD w,v=0;
|
||||
WORD wTestWriteData, wTestReadData;
|
||||
// Perform a reset via the PSP interface
|
||||
//set the clock to 33mhz: COCON[3..0] = "0001"
|
||||
//CLRREG(BaseAddress,ECON2, (ECON2_COCON3|ECON2_COCON2|ECON2_COCON1));
|
||||
//SETREG(BaseAddress,ECON2, ECON2_COCON0);
|
||||
|
||||
|
||||
do
|
||||
{
|
||||
|
||||
// Set and clear a few bits that clears themselves upon reset.
|
||||
// If EUDAST cannot be written to and your code gets stuck in this
|
||||
// loop, you have a hardware problem of some sort (SPI or PMP not
|
||||
// initialized correctly, I/O pins aren't connected or are
|
||||
// shorted to something, power isn't available, etc.)
|
||||
w= 0x1234;
|
||||
//do
|
||||
//{
|
||||
WRITEREG(BaseAddress,EUDAST, w);
|
||||
v=READREG(BaseAddress, EUDAST);
|
||||
printf("Read 0x%x at register 0x%x (should be 0x%x)\n",v,EUDAST,w);
|
||||
//} while(v != w);
|
||||
|
||||
// Issue a reset and wait for it to complete
|
||||
SETREG(BaseAddress,ECON2, ECON2_ETHRST);
|
||||
do{
|
||||
|
||||
delayCIA();
|
||||
v = READREG(BaseAddress,ESTAT);
|
||||
printf("Read 0x%x at register 0x%x\n",v,ESTAT);
|
||||
|
||||
}while((v & (ESTAT_CLKRDY | ESTAT_RSTDONE | ESTAT_PHYRDY)) != (ESTAT_CLKRDY | ESTAT_RSTDONE | ESTAT_PHYRDY));
|
||||
|
||||
// Check to see if the reset operation was successful by
|
||||
// checking if EUDAST went back to its reset default. This test
|
||||
// should always pass, but certain special conditions might make
|
||||
// this test fail, such as a PSP pin shorted to logic high.
|
||||
w=READREG(BaseAddress,EUDAST);
|
||||
printf("Read 0x%x at register 0x%x\n",w,EUDAST);
|
||||
} while(READREG(BaseAddress,EUDAST) != 0);
|
||||
|
||||
|
||||
// Really ensure reset is done and give some time for power to be stable
|
||||
for(i=0; i<1000; ++i){
|
||||
delayCIA();
|
||||
}
|
||||
|
||||
|
||||
// If using PSP, verify all address and data lines are working
|
||||
// Parallel direct addressing
|
||||
|
||||
// Initialize RAM contents with a random pattern and read back to verify
|
||||
// This step is critical if using a PSP interface since some functionality
|
||||
// may appear to work while a solder bridge or disconnect will cause
|
||||
// certain memory ranges to fail.
|
||||
|
||||
// Generate and write pattern
|
||||
for(w = 0; w < ENC100_RAM_SIZE; w += sizeof(wTestWriteData))
|
||||
{
|
||||
wTestWriteData = w;
|
||||
WRITEREG(BaseAddress, w, w);
|
||||
}
|
||||
|
||||
// Read back and verify random pattern
|
||||
|
||||
for(w = 0; w < ENC100_RAM_SIZE; w += sizeof(wTestWriteData))
|
||||
{
|
||||
wTestWriteData = w;
|
||||
wTestReadData = READREG(BaseAddress,w);
|
||||
|
||||
// See if the data matches. If your application gets stuck here,
|
||||
// it means you have a hardware failure. Check all of your PSP
|
||||
// address and data lines.
|
||||
if(wTestWriteData != wTestReadData)
|
||||
printf("Error checking memory at adress %lx! Expected $x - got %x\n",(BaseAddress+w),wTestWriteData,wTestReadData);
|
||||
|
||||
}
|
||||
return v;
|
||||
}
|
||||
|
||||
/*
|
||||
** **********************************************
|
||||
** LocateBoard()
|
||||
** **********************************************
|
||||
**
|
||||
** Locates Host Controller hardware
|
||||
**
|
||||
*/
|
||||
APTR LocateBoard(int manufactor, int product)
|
||||
{
|
||||
APTR board;
|
||||
|
||||
board = NULL; // Board not found (yet)
|
||||
|
||||
if ( ExpansionBase = OpenLibrary( "expansion.library", 36 ) ) {
|
||||
|
||||
struct ConfigDev *cfg;
|
||||
|
||||
|
||||
// *** Find board
|
||||
|
||||
if (cfg = FindConfigDev( NULL, manufactor, product ))
|
||||
{
|
||||
board = cfg->cd_BoardAddr; // Get board base adr.
|
||||
}
|
||||
|
||||
CloseLibrary( ExpansionBase );
|
||||
}
|
||||
|
||||
return( board ); // Return board ptr (or NULL)
|
||||
}
|
||||
|
||||
|
||||
main(int argc, char *argv[])
|
||||
{
|
||||
static int manufactor = 2588;
|
||||
static int product = 123;
|
||||
int v =0;
|
||||
APTR board = LocateBoard(manufactor,product);
|
||||
if(board){
|
||||
printf("Found board for manufactor/product %d/%d at address 0x%lx.\n",manufactor,product, board);
|
||||
v=SoftReset(board);
|
||||
printf("SoftReset returned %X\n",v);
|
||||
}else{
|
||||
printf("No board found for manufactor/product %d/%d.\n",manufactor,product);
|
||||
}
|
||||
}
|
||||
Binary file not shown.
@@ -0,0 +1,48 @@
|
||||
PROJECT= InitLAN
|
||||
DIR=
|
||||
SRCS= InitLAN.c
|
||||
HDRS=
|
||||
EXTRAS=
|
||||
PDEFAULT= InitLAN.h
|
||||
EXEDIR=
|
||||
OD=
|
||||
PRECOMP=
|
||||
TYPE= Normal
|
||||
RUN=
|
||||
CLIARGS=
|
||||
CFLAGS= -3.1 -R -// -f
|
||||
|
||||
#### AUTOMATICALLY GENERATED - DO NOT EDIT BELOW THIS LINE
|
||||
# $VER: Normal.DMakefile 3.2 (2.11.94)
|
||||
PROTOS= $(OD)$(PROJECT)-protos.h
|
||||
EXE= $(EXEDIR)$(PROJECT)
|
||||
COMPFLAGS = -no-env $(CFLAGS) $(OD:"*":-I*) $(PRECOMP:"*.h":"-HT:%1.m=%1.h") $(VMAKEPORT:"*":"-R0 *")
|
||||
PCOMPFILE = $(PRECOMP:"*.h":"T:*.m")
|
||||
|
||||
OBJS= $(SRCS:"*.c":"$(OD)*.o") $(SRCS:"*.a":"$(OD)*.o")
|
||||
|
||||
all: $(PCOMPFILE) $(PROTOS) $(EXE)
|
||||
|
||||
nopro: $(EXE)
|
||||
|
||||
$(EXE): $(OBJS)
|
||||
fwrite $(OD)$(PROJECT).lnktmp $(OBJS)
|
||||
dcc $(COMPFLAGS) @$(OD)$(PROJECT).lnktmp -o %(left)
|
||||
|
||||
$(OBJS) : $(SRCS)
|
||||
dcc %(right) -o %(left) -c $(COMPFLAGS)
|
||||
|
||||
$(PROTOS) : $(SRCS)
|
||||
-delete %(left)
|
||||
makeproto -o %(left) %(right)
|
||||
|
||||
$(PCOMPFILE:"":"CANT.EXIST.RULE") : $(HDRS)
|
||||
-delete %(left)
|
||||
|
||||
clean:
|
||||
-delete $(OBJS) $(PROTOS) $(PCOMPFILE)
|
||||
|
||||
relink: rmexe $(EXE)
|
||||
|
||||
rmexe:
|
||||
-delete $(EXE)
|
||||
Binary file not shown.
@@ -0,0 +1,39 @@
|
||||
#include <exec/memory.h>
|
||||
#include <exec/lists.h>
|
||||
#include <exec/nodes.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <libraries/expansion.h>
|
||||
#include <libraries/expansionbase.h>
|
||||
#include <libraries/configvars.h>
|
||||
#include <libraries/configregs.h>
|
||||
#include <dos/filehandler.h>
|
||||
#include <resources/filesysres.h>
|
||||
#include <clib/exec_protos.h>
|
||||
#include <clib/expansion_protos.h>
|
||||
#include "ENCX24J600.h"
|
||||
|
||||
#define VERSION_STRING "1.1"
|
||||
#define CIA_TST (*(volatile BYTE *)(0XBFE301)) //cia call 1.4micro sec
|
||||
#define CHP_TST (*(volatile WORD *)(0X000004)) //chip mem call 400ns
|
||||
#define WRITEREG(a,b,c) (*(volatile WORD *)((a)+(b)))=((WORD)(c))
|
||||
#define READREG(a,b) ((WORD)(*(volatile WORD *)((a)+(b))))
|
||||
#define SETREG(a,b,c) (*(volatile WORD *)((a)+(b)+(SET_OFFSET)))=((WORD)(c))
|
||||
#define CLRREG(a,b,c) (*(volatile WORD *)((a)+(b)+(CLR_OFFSET)))=((WORD)(c))
|
||||
|
||||
|
||||
struct Library *ExpansionBase=NULL;
|
||||
unsigned long hex2int(char *a);
|
||||
int SoftReset(APTR *BaseAddress);
|
||||
APTR LocateBoard(int manufactor, int product);
|
||||
|
||||
/**
|
||||
Function to wait for 1.4ms
|
||||
*/
|
||||
BYTE delayCIA();
|
||||
|
||||
/**
|
||||
Function to wait for 400ns
|
||||
*/
|
||||
|
||||
WORD delayShort();
|
||||
@@ -0,0 +1,2 @@
|
||||
InitLAN.o
|
||||
|
||||
@@ -0,0 +1,3 @@
|
||||
-2.0
|
||||
-dice
|
||||
-000
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
Exit code 20
|
||||
@@ -0,0 +1 @@
|
||||
|
||||
Reference in New Issue
Block a user