Dominick.Vansevenant/Zorro-LAN-IDE
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This commit is contained in:
MHeinrichs
2018-12-18 22:57:37 +01:00
parent a28f930027
commit 20aff1a84f
25 changed files with 8372 additions and 8270 deletions
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Logic/LAN_IDE/LAN_IDE_CP.rpt
+165 -159
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@@ -1,7 +1,7 @@
cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: LAN_IDE_CP Date: 12-18-2018, 10:22PM
Design Name: LAN_IDE_CP Date: 12-18-2018, 10:54PM
Device Used: XC95288XL-10-TQ144
Fitting Status: Successful
@@ -9,30 +9,30 @@ Fitting Status: Successful
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
194/288 ( 67%) 954 /1440 ( 66%) 446/864 ( 52%) 115/288 ( 40%) 109/117 ( 93%)
194/288 ( 67%) 958 /1440 ( 67%) 449/864 ( 52%) 115/288 ( 40%) 109/117 ( 93%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 22/54 40/90 8/ 8*
FB1 18/18* 22/54 42/90 8/ 8*
FB2 15/18 33/54 74/90 10/10*
FB3 2/18 2/54 1/90 3/ 5
FB4 15/18 33/54 90/90* 6/ 6*
FB5 12/18 33/54 77/90 7/ 8
FB6 17/18 34/54 49/90 8/ 8*
FB7 10/18 29/54 88/90 4/ 4*
FB6 15/18 34/54 42/90 8/ 8*
FB7 11/18 29/54 90/90* 4/ 4*
FB8 11/18 34/54 66/90 5/ 5*
FB9 10/18 31/54 88/90 8/ 9
FB10 17/18 33/54 50/90 10/10*
FB10 15/18 33/54 48/90 10/10*
FB11 14/18 30/54 75/90 7/ 7*
FB12 11/18 33/54 22/90 6/ 6*
FB13 9/18 33/54 65/90 6/ 6*
FB14 5/18 8/54 8/90 5/ 8
FB14 8/18 11/54 17/90 5/ 8
FB15 11/18 32/54 83/90 8/ 9
FB16 17/18 26/54 78/90 8/ 8*
----- ----- ----- -----
194/288 446/864 954/1440 109/117
194/288 449/864 958/1440 109/117
* - Resource is exhausted
@@ -199,7 +199,7 @@ LAN_RST_SM_FSM_FFd3 3 3 FB1_9 STD RESET
LAN_RST_SM_FSM_FFd2 3 4 FB1_11 STD RESET
LAN_IRQ_OUT 3 4 FB1_13 STD RESET
LAN_SM_FSM_FFd1 4 6 FB1_16 STD RESET
LAN_READY 5 7 FB1_18 STD RESET
LAN_READY 7 7 FB1_18 STD RESET
LAN_BASEADR<0> 9 17 FB2_1 STD RESET
LAN_BASEADR<11> 9 17 FB2_4 STD RESET
LAN_BASEADR<12> 9 17 FB2_7 STD RESET
@@ -220,9 +220,7 @@ LAN_BASEADR<14> 9 17 FB5_7 STD RESET
LAN_BASEADR<15> 9 17 FB5_8 STD RESET
$OpTx$FX_DC$118__$INT 4 8 FB5_18 STD
$OpTx$INV$205 16 16 FB6_1 STD
Z3_ADR_0 3 3 FB6_4 STD RESET
Z3_ADR<9> 3 3 FB6_7 STD RESET
Z3_ADR<8> 3 3 FB6_9 STD RESET
N0$BUF7/N0$BUF7_TRST__$INT 2 4 FB6_9 STD
Z3_ADR<7> 3 3 FB6_11 STD RESET
Z3_ADR<6> 3 3 FB6_12 STD RESET
Z3_ADR<5> 3 3 FB6_13 STD RESET
@@ -230,10 +228,11 @@ Z3_ADR<4> 3 3 FB6_15 STD RESET
Z3_ADR<3> 3 3 FB6_16 STD RESET
Z3_ADR<2> 3 3 FB6_17 STD RESET
D_OUT<6> 11 14 FB7_1 STD SET
$OpTx$FX_DC$112 2 5 FB7_2 STD
$OpTx$FX_SC$119__$INT 4 8 FB7_7 STD
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
$OpTx$FX_SC$119__$INT 4 8 FB7_7 STD
LAN_BASEADR<9> 9 17 FB7_9 STD RESET
LAN_BASEADR<8> 9 17 FB7_11 STD RESET
LAN_BASEADR<7> 9 17 FB7_13 STD RESET
@@ -252,10 +251,8 @@ DQ_DATA<6> 13 13 FB9_9 STD RESET
Z3_A_LOW 9 9 FB9_13 STD RESET
DQ_DATA<15> 13 13 FB9_16 STD RESET
DQ_DATA<14> 13 13 FB9_18 STD RESET
N0$BUF7/N0$BUF7_TRST__$INT 2 4 FB10_4 STD
$OpTx$FX_DC$112 2 5 FB10_7 STD
LAN_INT_ENABLE 3 7 FB10_9 STD RESET
LAN_SM_RST 4 8 FB10_13 STD RESET
LAN_SM_RST 4 8 FB10_9 STD RESET
LAN_INT_ENABLE 5 10 FB10_13 STD RESET
D_OUT<7> 5 12 FB10_15 STD SET
D_OUT<3> 5 11 FB10_16 STD SET
D_OUT<0> 5 13 FB10_18 STD SET
@@ -273,15 +270,18 @@ LAN_D_INIT<1> 2 2 FB12_16 STD RESET
LAN_A_INIT<6> 2 2 FB12_17 STD SET
AUTOCONFIG_ACCESS 3 21 FB12_18 STD RESET
DQ_DATA<1> 13 13 FB13_1 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
DQ_DATA<3> 13 13 FB13_6 STD RESET
DQ_DATA<8> 13 13 FB13_12 STD RESET
LAN_RD_S 4 6 FB13_15 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
DQ_DATA<9> 13 13 FB13_16 STD RESET
LAN_A_INIT<3> 1 1 FB13_18 STD SET
Z3_ADR_1 3 3 FB14_18 STD RESET
Z3_ADR_1 3 3 FB14_13 STD RESET
Z3_ADR_0 3 3 FB14_16 STD RESET
Z3_ADR<9> 3 3 FB14_17 STD RESET
Z3_ADR<8> 3 3 FB14_18 STD RESET
DQ_DATA<12> 13 13 FB15_1 STD RESET
LAN_SM_FSM_FFd3 7 10 FB15_2 STD RESET
Z3_DATA<31> 4 8 FB15_4 STD RESET
@@ -361,8 +361,8 @@ LAN_IRQ_OUT 3 0 0 2 FB1_13 (b) (b)
IDE_A<2> 0 0 0 5 FB1_14 25 I/O O
IDE_A<1> 0 0 0 5 FB1_15 26 I/O O
LAN_SM_FSM_FFd1 4 0 0 1 FB1_16 (b) (b)
IDE_R 0 0 0 5 FB1_17 27 I/O O
LAN_READY 5 0 0 0 FB1_18 (b) (b)
IDE_R 0 0 \/2 3 FB1_17 27 I/O O
LAN_READY 7 2<- 0 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_SC$119__$INT 9: LAN_RST_SM_FSM_FFd1 16: LAN_SM_RST
@@ -606,12 +606,13 @@ Name Pt Pt Pt Pt # Type Use
$OpTx$INV$205 16 11<- 0 0 FB6_1 (b) (b)
LAN_CFG<2> 0 0 /\4 1 FB6_2 135 I/O O
A_LAN<12> 1 0 0 4 FB6_3 136 I/O O
Z3_ADR_0 3 0 0 2 FB6_4 (b) (b)
(unused) 0 0 0 5 FB6_4 (b)
A_LAN<13> 1 0 0 4 FB6_5 137 I/O O
A_LAN<10> 1 0 0 4 FB6_6 138 I/O O
Z3_ADR<9> 3 0 0 2 FB6_7 (b) (b)
(unused) 0 0 0 5 FB6_7 (b)
A_LAN<11> 1 0 0 4 FB6_8 139 I/O O
Z3_ADR<8> 3 0 0 2 FB6_9 (b) (b)
N0$BUF7/N0$BUF7_TRST__$INT
2 0 0 3 FB6_9 (b) (b)
A_LAN<8> 1 0 0 4 FB6_10 140 I/O O
Z3_ADR<7> 3 0 0 2 FB6_11 (b) (b)
Z3_ADR<6> 3 0 0 2 FB6_12 (b) (b)
@@ -623,38 +624,37 @@ Z3_ADR<2> 3 0 \/2 0 FB6_17 (b) (b)
(unused) 0 0 \/5 0 FB6_18 (b) (b)
Signals Used by Logic in Function Block
1: A<2> 13: LAN_BASEADR<5> 24: A<20>.PIN
2: A<4> 14: LAN_BASEADR<7> 25: A<21>.PIN
3: A<5> 15: A<10>.PIN 26: A<16>.PIN
4: A<6> 16: A<11>.PIN 27: RESET
5: A<7> 17: A<17>.PIN 28: Z3_ADR<10>
6: FCS 18: A<23>.PIN 29: Z3_ADR<11>
7: LAN_BASEADR<0> 19: A<18>.PIN 30: Z3_ADR<12>
8: LAN_BASEADR<14> 20: A<19>.PIN 31: Z3_ADR<7>
9: LAN_BASEADR<1> 21: A<8>.PIN 32: Z3_ADR<8>
10: LAN_BASEADR<2> 22: A<9>.PIN 33: Z3_ADR<9>
11: LAN_BASEADR<3> 23: D<14>.PIN 34: Z3_ADR_1/Z3_ADR_1_SETF__$INT
12: LAN_BASEADR<4>
1: AUTOCONFIG_ACCESS 13: LAN_BASEADR<4> 24: A<20>.PIN
2: A<4> 14: LAN_BASEADR<5> 25: A<21>.PIN
3: A<5> 15: LAN_BASEADR<7> 26: A<16>.PIN
4: A<6> 16: LAN_READY 27: RESET
5: A<7> 17: A<17>.PIN 28: Z3_ADR<10>
6: CONFIG_READY 18: A<23>.PIN 29: Z3_ADR<11>
7: FCS 19: A<18>.PIN 30: Z3_ADR<12>
8: LAN_BASEADR<0> 20: A<19>.PIN 31: Z3_ADR<7>
9: LAN_BASEADR<14> 21: A<8>.PIN 32: Z3_ADR<8>
10: LAN_BASEADR<1> 22: A<9>.PIN 33: Z3_ADR<9>
11: LAN_BASEADR<2> 23: D<14>.PIN 34: Z3_ADR_1/Z3_ADR_1_SETF__$INT
12: LAN_BASEADR<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
$OpTx$INV$205 ......XXXXXXXX..XXXX..XXXX.............. 16
$OpTx$INV$205 .......XXXXXXXX.XXXX..XXXX.............. 16
LAN_CFG<2> ........................................ 0
A_LAN<12> ..........................X.X........... 2
Z3_ADR_0 X....X...........................X...... 3
A_LAN<13> ..........................X..X.......... 2
A_LAN<10> ..........................X.....X....... 2
Z3_ADR<9> .....X.........X.................X...... 3
A_LAN<11> ..........................XX............ 2
Z3_ADR<8> .....X........X..................X...... 3
N0$BUF7/N0$BUF7_TRST__$INT
X....XX........X........................ 4
A_LAN<8> ..........................X...X......... 2
Z3_ADR<7> .....X...............X...........X...... 3
Z3_ADR<6> .....X..............X............X...... 3
Z3_ADR<5> ....XX...........................X...... 3
Z3_ADR<7> ......X..............X...........X...... 3
Z3_ADR<6> ......X.............X............X...... 3
Z3_ADR<5> ....X.X..........................X...... 3
A_LAN<9> ..........................X....X........ 2
Z3_ADR<4> ...X.X...........................X...... 3
Z3_ADR<3> ..X..X...........................X...... 3
Z3_ADR<2> .X...X...........................X...... 3
Z3_ADR<4> ...X..X..........................X...... 3
Z3_ADR<3> ..X...X..........................X...... 3
Z3_ADR<2> .X....X..........................X...... 3
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
@@ -663,11 +663,11 @@ Number of signals used by logic mapping into function block: 29
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
D_OUT<6> 11 6<- 0 0 FB7_1 (b) (b)
(unused) 0 0 /\5 0 FB7_2 (b) (b)
D<13> 9 4<- 0 0 FB7_3 45 I/O I/O
(unused) 0 0 /\4 1 FB7_4 (b) (b)
D<14> 9 4<- 0 0 FB7_5 46 I/O I/O
(unused) 0 0 /\4 1 FB7_6 (b) (b)
$OpTx$FX_DC$112 2 2<- /\5 0 FB7_2 (b) (b)
D<13> 9 6<- /\2 0 FB7_3 45 I/O I/O
(unused) 0 0 /\5 0 FB7_4 (b) (b)
D<14> 9 5<- /\1 0 FB7_5 46 I/O I/O
(unused) 0 0 /\5 0 FB7_6 (b) (b)
$OpTx$FX_SC$119__$INT
4 0 \/1 0 FB7_7 (b) (b)
(unused) 0 0 \/5 0 FB7_8 (b) (b)
@@ -697,6 +697,7 @@ Signals Used by Logic in Function Block
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
D_OUT<6> .XXX...X....X...X.XXXXXXXX.............. 14
$OpTx$FX_DC$112 ..XX...X....X.....X..................... 5
D<13> X.XXX..XX...X....XX.......X............. 10
D<14> X.XX.X.XX...X....XX........X............ 10
$OpTx$FX_SC$119__$INT
@@ -821,17 +822,16 @@ Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB10_1 (b)
DQ<1> 3 0 0 2 FB10_2 117 I/O I/O
DQ<0> 2 0 0 3 FB10_3 118 I/O I/O
N0$BUF7/N0$BUF7_TRST__$INT
2 0 0 3 FB10_4 (b) (b)
(unused) 0 0 0 5 FB10_4 (b)
DQ<3> 2 0 0 3 FB10_5 119 I/O I/O
DQ<2> 2 0 0 3 FB10_6 120 I/O I/O
$OpTx$FX_DC$112 2 0 0 3 FB10_7 (b) (b)
(unused) 0 0 0 5 FB10_7 (b)
DQ<5> 2 0 0 3 FB10_8 121 I/O I/O
LAN_INT_ENABLE 3 0 0 2 FB10_9 (b) (b)
LAN_SM_RST 4 0 0 1 FB10_9 (b) (b)
DQ<4> 3 0 0 2 FB10_10 124 I/O I/O
DQ<7> 2 0 0 3 FB10_11 125 I/O I/O
DQ<6> 2 0 0 3 FB10_12 126 I/O I/O
LAN_SM_RST 4 0 0 1 FB10_13 (b) (b)
LAN_INT_ENABLE 5 0 0 0 FB10_13 (b) (b)
DQ<8> 3 0 0 2 FB10_14 128 I/O I/O
D_OUT<7> 5 0 0 0 FB10_15 (b) (b)
D_OUT<3> 5 0 0 0 FB10_16 (b) (b)
@@ -839,38 +839,35 @@ DQ<10> 3 0 0 2 FB10_17 129 I/O I/O
D_OUT<0> 5 0 0 0 FB10_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$118__$INT 12: DQ_DATA<7> 23: RESET
2: AUTOCONFIG_ACCESS 13: DQ_DATA<8> 24: RW
3: CONFIG_READY 14: DS0 25: UDS
4: DQ_DATA<0> 15: DS1 26: Z3_ADR<13>
5: DQ_DATA<10> 16: FCS 27: Z3_ADR<2>
6: DQ_DATA<1> 17: LAN_ACCESS 28: Z3_ADR<3>
7: DQ_DATA<2> 18: LAN_D_INIT<1> 29: Z3_ADR<4>
8: DQ_DATA<3> 19: LAN_D_INIT<8> 30: Z3_ADR<5>
9: DQ_DATA<4> 20: LAN_READY 31: Z3_ADR<6>
10: DQ_DATA<5> 21: LDS 32: Z3_ADR_0
11: DQ_DATA<6> 22: D<15>.PIN 33: Z3_ADR_1
1: $OpTx$FX_DC$118__$INT 12: DQ_DATA<8> 23: RESET
2: AUTOCONFIG_ACCESS 13: DS0 24: RW
3: DQ_DATA<0> 14: DS1 25: UDS
4: DQ_DATA<10> 15: FCS 26: Z3_ADR<13>
5: DQ_DATA<1> 16: LAN_ACCESS 27: Z3_ADR<2>
6: DQ_DATA<2> 17: LAN_D_INIT<1> 28: Z3_ADR<3>
7: DQ_DATA<3> 18: LAN_D_INIT<8> 29: Z3_ADR<4>
8: DQ_DATA<4> 19: LAN_INT_ENABLE 30: Z3_ADR<5>
9: DQ_DATA<5> 20: LDS 31: Z3_ADR<6>
10: DQ_DATA<6> 21: A<23>.PIN 32: Z3_ADR_0
11: DQ_DATA<7> 22: D<15>.PIN 33: Z3_ADR_1
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DQ<1> X....X...........X....X................. 4
DQ<0> X..X..................X................. 3
N0$BUF7/N0$BUF7_TRST__$INT
.XX............X...X.................... 4
DQ<3> X......X..............X................. 3
DQ<2> X.....X...............X................. 3
$OpTx$FX_DC$112 .............XXX....X...X............... 5
DQ<5> X........X............X................. 3
LAN_INT_ENABLE ...............XX....XXXXX.............. 7
DQ<4> X.......X........X....X................. 4
DQ<7> X..........X..........X................. 3
DQ<6> X.........X...........X................. 3
LAN_SM_RST .............XXXX...X.X.XX.............. 8
DQ<8> X...........X.....X...X................. 4
D_OUT<7> .X...........XXX....X.X.X..XXXX.X....... 12
D_OUT<3> .X...........XXX....X.X.X..XXX..X....... 11
DQ<10> X...X.............X...X................. 4
D_OUT<0> .X...........XXX....X.X.X.XXXX.XX....... 13
DQ<1> X...X...........X.....X................. 4
DQ<0> X.X...................X................. 3
DQ<3> X.....X...............X................. 3
DQ<2> X....X................X................. 3
DQ<5> X.......X.............X................. 3
LAN_SM_RST ............XXXX...X..X.XX.............. 8
DQ<4> X......X........X.....X................. 4
DQ<7> X.........X...........X................. 3
DQ<6> X........X............X................. 3
LAN_INT_ENABLE .............XXX..X.XXXXXX.............. 10
DQ<8> X..........X.....X....X................. 4
D_OUT<7> .X..........XXX....X..X.X..XXXX.X....... 12
D_OUT<3> .X..........XXX....X..X.X..XXX..X....... 11
DQ<10> X..X.............X....X................. 4
D_OUT<0> .X..........XXX....X..X.X.XXXX.XX....... 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB11 ***********************************
@@ -1032,8 +1029,8 @@ LAN_A_INIT<3> ..............................X......... 1
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB14 ***********************************
Number of function block inputs used/remaining: 8/46
Number of signals used by logic mapping into function block: 8
Number of function block inputs used/remaining: 11/43
Number of signals used by logic mapping into function block: 11
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB14_1 (b)
@@ -1048,25 +1045,29 @@ OVR 0 0 0 5 FB14_3 100 I/O O
(unused) 0 0 0 5 FB14_10 104 I/O I
CFOUT 3 0 0 2 FB14_11 105 I/O O
(unused) 0 0 0 5 FB14_12 (b)
(unused) 0 0 0 5 FB14_13 (b)
Z3_ADR_1 3 0 0 2 FB14_13 (b) (b)
SLAVE 2 0 0 3 FB14_14 106 I/O O
OWN 0 0 0 5 FB14_15 107 I/O O
(unused) 0 0 0 5 FB14_16 (b)
(unused) 0 0 0 5 FB14_17 (b)
Z3_ADR_1 3 0 0 2 FB14_18 (b) (b)
Z3_ADR_0 3 0 0 2 FB14_16 (b) (b)
Z3_ADR<9> 3 0 0 2 FB14_17 (b) (b)
Z3_ADR<8> 3 0 0 2 FB14_18 (b) (b)
Signals Used by Logic in Function Block
1: AUTOBOOT_OFF 4: A<3> 7: RESET
2: AUTOCONFIG_ACCESS 5: FCS 8: Z3_ADR_1/Z3_ADR_1_SETF__$INT
3: AUTO_CONFIG_DONE_CYCLE 6: LAN_ACCESS
1: AUTOBOOT_OFF 5: A<3> 9: A<11>.PIN
2: AUTOCONFIG_ACCESS 6: FCS 10: RESET
3: AUTO_CONFIG_DONE_CYCLE 7: LAN_ACCESS 11: Z3_ADR_1/Z3_ADR_1_SETF__$INT
4: A<2> 8: A<10>.PIN
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
OVR ........................................ 0
CFOUT X.X.X.X................................. 4
SLAVE .X..XX.................................. 3
CFOUT X.X..X...X.............................. 4
Z3_ADR_1 ....XX....X............................. 3
SLAVE .X...XX................................. 3
OWN ........................................ 0
Z3_ADR_1 ...XX..X................................ 3
Z3_ADR_0 ...X.X....X............................. 3
Z3_ADR<9> .....X..X.X............................. 3
Z3_ADR<8> .....X.X..X............................. 3
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB15 ***********************************
@@ -1355,10 +1356,10 @@ AUTO_CONFIG_DONE_CYCLE_T <= ((NOT RW AND NOT FCS AND NOT UDS AND NOT AUTO_CONFIG
OR (NOT RW AND NOT FCS AND NOT LDS AND NOT AUTO_CONFIG_DONE_CYCLE AND
NOT Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND
NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT AUTO_CONFIG_DONE_CYCLE AND
OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT AUTO_CONFIG_DONE_CYCLE AND
NOT Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND
NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT AUTO_CONFIG_DONE_CYCLE AND
OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT AUTO_CONFIG_DONE_CYCLE AND
NOT Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND
NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
@@ -1424,16 +1425,16 @@ CP_WE <= '1';
D_I(0) <= NOT (((RW AND NOT FCS AND NOT UDS AND NOT Z3_DATA(16) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT LDS AND NOT Z3_DATA(16) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(16) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(16) AND LAN_ACCESS)));
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(16) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(16) AND LAN_ACCESS)));
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
D_OE(0) <= NOT $OpTx$FX_SC$119__$INT;
D_I(1) <= NOT (((RW AND NOT FCS AND NOT UDS AND NOT Z3_DATA(17) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT LDS AND NOT Z3_DATA(17) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(17) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(17) AND LAN_ACCESS)));
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(17) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(17) AND LAN_ACCESS)));
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
D_OE(1) <= NOT $OpTx$FX_SC$119__$INT;
@@ -1480,8 +1481,8 @@ D_OE(6) <= NOT $OpTx$FX_SC$119__$INT;
D_I(7) <= NOT (((RW AND NOT FCS AND NOT UDS AND NOT Z3_DATA(23) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT LDS AND NOT Z3_DATA(23) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(23) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(23) AND LAN_ACCESS)));
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(23) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(23) AND LAN_ACCESS)));
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
D_OE(7) <= NOT $OpTx$FX_SC$119__$INT;
@@ -1500,60 +1501,60 @@ D_OE(8) <= NOT $OpTx$FX_SC$119__$INT;
D_I(9) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(25) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(25) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(25) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(25) AND LAN_ACCESS)
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(1))
OR (NOT RW AND D_OUT(1))
OR (FCS AND D_OUT(1))
OR (NOT LAN_ACCESS AND D_OUT(1))
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(25) AND LAN_ACCESS));
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(25) AND LAN_ACCESS));
D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
D_OE(9) <= NOT $OpTx$FX_SC$119__$INT;
D_I(10) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(26) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(26) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(26) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(26) AND LAN_ACCESS)
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(2))
OR (NOT RW AND D_OUT(2))
OR (FCS AND D_OUT(2))
OR (NOT LAN_ACCESS AND D_OUT(2))
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(26) AND LAN_ACCESS));
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(26) AND LAN_ACCESS));
D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
D_OE(10) <= NOT $OpTx$FX_SC$119__$INT;
D_I(11) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(27) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(27) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(27) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(27) AND LAN_ACCESS)
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(3))
OR (NOT RW AND D_OUT(3))
OR (FCS AND D_OUT(3))
OR (NOT LAN_ACCESS AND D_OUT(3))
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(27) AND LAN_ACCESS));
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(27) AND LAN_ACCESS));
D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
D_OE(11) <= NOT $OpTx$FX_SC$119__$INT;
D_I(12) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(28) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(28) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(28) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(28) AND LAN_ACCESS)
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(4))
OR (NOT RW AND D_OUT(4))
OR (FCS AND D_OUT(4))
OR (NOT LAN_ACCESS AND D_OUT(4))
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(28) AND LAN_ACCESS));
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(28) AND LAN_ACCESS));
D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
D_OE(12) <= NOT $OpTx$FX_SC$119__$INT;
D_I(13) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(29) AND LAN_ACCESS)
D_I(13) <= ((D_14_IOBUFE.EXP)
OR (NOT RW AND D_OUT(5))
OR (RW AND NOT FCS AND NOT UDS AND Z3_DATA(29) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(29) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(29) AND LAN_ACCESS)
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(5))
OR (NOT RW AND D_OUT(5))
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(29) AND LAN_ACCESS)
OR (FCS AND D_OUT(5))
OR (NOT LAN_ACCESS AND D_OUT(5))
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(29) AND LAN_ACCESS));
OR (NOT LAN_ACCESS AND D_OUT(5)));
D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
D_OE(13) <= NOT $OpTx$FX_SC$119__$INT;
@@ -1561,23 +1562,23 @@ D_OE(13) <= NOT $OpTx$FX_SC$119__$INT;
D_I(14) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(30) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(30) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(30) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(30) AND LAN_ACCESS)
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(6))
OR (NOT RW AND D_OUT(6))
OR (FCS AND D_OUT(6))
OR (NOT LAN_ACCESS AND D_OUT(6))
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(30) AND LAN_ACCESS));
OR (NOT LAN_ACCESS AND D_OUT(6)));
D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
D_OE(14) <= NOT $OpTx$FX_SC$119__$INT;
D_I(15) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(31) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(31) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(31) AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(31) AND LAN_ACCESS)
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(7))
OR (NOT RW AND D_OUT(7))
OR (FCS AND D_OUT(7))
OR (NOT LAN_ACCESS AND D_OUT(7))
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(31) AND LAN_ACCESS));
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(31) AND LAN_ACCESS));
D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
D_OE(15) <= NOT $OpTx$FX_SC$119__$INT;
@@ -1776,7 +1777,7 @@ DQ_DATA_D(4) <= ((Z3_DATA(31).EXP)
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(4)));
FDCPE_DQ_DATA5: FDCPE port map (DQ_DATA(5),DQ_DATA_D(5),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(5) <= ((EXP67_.EXP)
DQ_DATA_D(5) <= ((EXP66_.EXP)
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(5))
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(5))
OR (LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
@@ -1965,7 +1966,7 @@ DQ_DATA_D(13) <= ((LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(13)));
FDCPE_DQ_DATA14: FDCPE port map (DQ_DATA(14),DQ_DATA_D(14),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(14) <= ((EXP49_.EXP)
DQ_DATA_D(14) <= ((EXP48_.EXP)
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(14))
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(14))
OR (LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
@@ -2010,7 +2011,7 @@ DQ_SWAP_D <= ((NOT Z3)
OR (NOT D(15).PIN AND LAN_BASEADR(15))
OR (NOT A(13).PIN)
OR (NOT A(14).PIN)
OR (EXP46_.EXP)
OR (EXP45_.EXP)
OR (D(9).PIN AND NOT LAN_BASEADR(9))
OR (NOT D(9).PIN AND LAN_BASEADR(9))
OR (D(11).PIN AND NOT LAN_BASEADR(11)));
@@ -2042,21 +2043,21 @@ D_OUT_D(1) <= ((Z3_ADR(3))
OR (Z3_ADR_1 AND Z3_ADR_0));
FDCPE_D_OUT2: FDCPE port map (D_OUT(2),D_OUT_D(2),CLK_EXT,'0',NOT RESET);
D_OUT_D(2) <= ((NOT FCS AND NOT UDS AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
D_OUT_D(2) <= ((NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT FCS AND NOT LDS AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT FCS AND NOT LDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT FCS AND NOT DS1 AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT FCS AND NOT DS1 AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT FCS AND NOT DS0 AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT FCS AND NOT DS0 AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT FCS AND NOT UDS AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT FCS AND NOT DS1 AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT FCS AND NOT DS1 AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)));
FDCPE_D_OUT3: FDCPE port map (D_OUT(3),D_OUT_D(3),CLK_EXT,'0',NOT RESET);
@@ -2208,8 +2209,6 @@ D_OUT_D(7) <= ((NOT FCS AND NOT UDS AND NOT Z3_ADR_1 AND Z3_ADR(6) AND
@@ -2248,7 +2247,7 @@ LAN_ACCESS_D <= ((NOT Z3)
OR (D(11).PIN AND NOT LAN_BASEADR(11))
OR (NOT D(11).PIN AND LAN_BASEADR(11))
OR (D(15).PIN AND NOT LAN_BASEADR(15))
OR (EXP45_.EXP)
OR (EXP44_.EXP)
OR (D(12).PIN AND NOT LAN_BASEADR(12))
OR (NOT D(12).PIN AND LAN_BASEADR(12))
OR (D(10).PIN AND NOT LAN_BASEADR(10))
@@ -2469,10 +2468,10 @@ LAN_BASEADR_T(7) <= ((NOT RW AND NOT FCS AND NOT UDS AND D(7).PIN AND NOT LAN_BA
FTCPE_LAN_BASEADR8: FTCPE port map (LAN_BASEADR(8),LAN_BASEADR_T(8),CLK_EXT,'0',NOT RESET);
LAN_BASEADR_T(8) <= ((LAN_BASEADR(9).EXP)
OR (D(8).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_BASEADR(8) AND
OR (D(8).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_BASEADR(8) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (D(8).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND NOT LAN_BASEADR(8) AND
OR (D(8).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_BASEADR(8) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT D(8).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_BASEADR(8) AND
@@ -2481,10 +2480,10 @@ LAN_BASEADR_T(8) <= ((LAN_BASEADR(9).EXP)
OR (NOT D(8).PIN AND NOT RW AND NOT FCS AND NOT LDS AND LAN_BASEADR(8) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT D(8).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND LAN_BASEADR(8) AND
OR (NOT D(8).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND LAN_BASEADR(8) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT D(8).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND LAN_BASEADR(8) AND
OR (NOT D(8).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND LAN_BASEADR(8) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
@@ -2499,16 +2498,16 @@ LAN_BASEADR_T(9) <= (($OpTx$FX_SC$119__$INT.EXP)
OR (D(9).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND NOT LAN_BASEADR(9) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT D(9).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_BASEADR(9) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT D(9).PIN AND NOT RW AND NOT FCS AND NOT LDS AND LAN_BASEADR(9) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT D(9).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND LAN_BASEADR(9) AND
OR (NOT D(9).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND LAN_BASEADR(9) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT D(9).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND LAN_BASEADR(9) AND
OR (NOT D(9).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_BASEADR(9) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT D(9).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND LAN_BASEADR(9) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
@@ -2591,18 +2590,18 @@ LAN_BASEADR_T(12) <= ((D(12).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
FTCPE_LAN_BASEADR13: FTCPE port map (LAN_BASEADR(13),LAN_BASEADR_T(13),CLK_EXT,'0',NOT RESET);
LAN_BASEADR_T(13) <= ((D(13).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_BASEADR(13) AND
LAN_BASEADR_T(13) <= ((D(13).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_BASEADR(13) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (D(13).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND NOT LAN_BASEADR(13) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (D(13).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_BASEADR(13) AND
OR (D(13).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_BASEADR(13) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (D(13).PIN AND NOT RW AND NOT FCS AND NOT LDS AND NOT LAN_BASEADR(13) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (D(13).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND NOT LAN_BASEADR(13) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
OR (NOT D(13).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_BASEADR(13) AND
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
@@ -2699,8 +2698,15 @@ FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),LAN_RST_SM_FSM_FFd1,CLK_EXT,RES
FDCPE_LAN_D_INIT8: FDCPE port map (LAN_D_INIT(8),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0');
FDCPE_LAN_INT_ENABLE: FDCPE port map (LAN_INT_ENABLE,D(15).PIN,CLK_EXT,NOT RESET,'0',LAN_INT_ENABLE_CE);
LAN_INT_ENABLE_CE <= (NOT RW AND NOT FCS AND NOT UDS AND LAN_ACCESS AND Z3_ADR(13));
FTCPE_LAN_INT_ENABLE: FTCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_T,CLK_EXT,NOT RESET,'0');
LAN_INT_ENABLE_T <= ((D(15).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_INT_ENABLE AND
LAN_ACCESS AND Z3_ADR(13))
OR (NOT D(15).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_INT_ENABLE AND
LAN_ACCESS AND Z3_ADR(13))
OR (NOT RW AND NOT FCS AND UDS AND NOT DS1 AND LAN_INT_ENABLE AND
LAN_ACCESS AND Z3_ADR(13) AND NOT A(23).PIN)
OR (NOT RW AND NOT FCS AND UDS AND NOT DS1 AND NOT LAN_INT_ENABLE AND
LAN_ACCESS AND Z3_ADR(13) AND A(23).PIN));
FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,CLK_EXT,'0',NOT RESET);
@@ -2718,14 +2724,14 @@ LAN_RD_S_D <= ((RW AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2));
FDCPE_LAN_READY: FDCPE port map (LAN_READY,LAN_READY_D,CLK_EXT,LAN_SM_RST,'0');
LAN_READY_D <= ((NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
LAN_READY_D <= ((DS1 AND DS0 AND LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2)
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd3)
OR (LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3)
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd1)
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd3)
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd3)
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3));
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3));
FTCPE_LAN_RST_SM_FSM_FFd1: FTCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_T,CLK_EXT,RESET,'0');
LAN_RST_SM_FSM_FFd1_T <= (NOT LAN_RST_SM_FSM_FFd1 AND LAN_RST_SM_FSM_FFd2 AND