Dominick.Vansevenant/Zorro-LAN-IDE
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new style of autoconfig

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This commit is contained in:
MHeinrichs
2016-12-28 23:47:02 +01:00
parent 53aacaf617
commit 172fc9a0fd
70 changed files with 24589 additions and 11642 deletions
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Logic/LAN_IDE/LAN_IDE_CP.syr
+36 -34
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@@ -89,6 +89,8 @@ Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <beh
* HDL Analysis *
=========================================================================
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
INFO:Xst:2679 - Register <CP_BASEADR> in unit <LAN_IDE_CP> has a constant value of 11111111 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <SHUT_UP<1>> in unit <LAN_IDE_CP> has a constant value of 1 during circuit operation. The register is replaced by logic.
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
@@ -97,6 +99,7 @@ Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
=========================================================================
Performing bidirectional port resolution...
INFO:Xst:2679 - Register <cp> in unit <LAN_IDE_CP> has a constant value of 0 during circuit operation. The register is replaced by logic.
Synthesizing Unit <LAN_IDE_CP>.
Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
@@ -110,6 +113,7 @@ WARNING:Xst:647 - Input <Z3> is never used. This port will be preserved and left
WARNING:Xst:647 - Input <CLK_EXT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <OVR> is never assigned.
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <LAN_INT_ENABLE> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Found 16-bit tristate buffer for signal <D>.
@@ -121,12 +125,9 @@ WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected sig
Found 3-bit register for signal <AUTO_CONFIG_DONE>.
Found 3-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
Found 1-bit register for signal <autoconfig>.
Found 1-bit register for signal <cp>.
Found 8-bit comparator equal for signal <cp$cmp_eq0000> created at line 141.
Found 8-bit register for signal <CP_BASEADR>.
Found 4-bit register for signal <Dout1>.
Found 1-bit register for signal <ide>.
Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 135.
Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 141.
Found 8-bit register for signal <IDE_BASEADR>.
Found 1-bit register for signal <IDE_ENABLE>.
Found 1-bit register for signal <IDE_R_S>.
@@ -134,12 +135,12 @@ WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected sig
Found 1-bit register for signal <lan>.
Found 8-bit comparator equal for signal <lan$cmp_eq0000> created at line 129.
Found 8-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_INT_ENABLE>.
Found 1-bit register for signal <ROM_OE_S>.
Found 3-bit register for signal <SHUT_UP>.
Found 1-bit register for signal <SHUT_UP<2>>.
Found 1-bit register for signal <SHUT_UP<0>>.
Summary:
inferred 5 D-type flip-flop(s).
inferred 3 Comparator(s).
inferred 3 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 1 Xor(s).
inferred 35 Tristate(s).
Unit <LAN_IDE_CP> synthesized.
@@ -149,13 +150,13 @@ Unit <LAN_IDE_CP> synthesized.
HDL Synthesis Report
Macro Statistics
# Registers : 20
1-bit register : 15
# Registers : 16
1-bit register : 12
3-bit register : 1
4-bit register : 1
8-bit register : 3
# Comparators : 3
8-bit comparator equal : 3
8-bit register : 2
# Comparators : 2
8-bit comparator equal : 2
# Tristates : 5
1-bit tristate buffer : 3
16-bit tristate buffer : 2
@@ -173,10 +174,10 @@ Macro Statistics
Advanced HDL Synthesis Report
Macro Statistics
# Registers : 5
Flip-Flops : 5
# Comparators : 3
8-bit comparator equal : 3
# Registers : 3
Flip-Flops : 3
# Comparators : 2
8-bit comparator equal : 2
=========================================================================
@@ -216,22 +217,23 @@ Design Statistics
# IOs : 116
Cell Usage :
# BELS : 373
# AND2 : 83
# AND3 : 23
# BELS : 379
# AND2 : 99
# AND3 : 22
# AND4 : 1
# GND : 1
# INV : 148
# OR2 : 87
# OR3 : 2
# OR4 : 3
# INV : 147
# OR2 : 83
# OR3 : 7
# OR4 : 1
# VCC : 1
# XOR2 : 25
# FlipFlops/Latches : 46
# XOR2 : 17
# FlipFlops/Latches : 35
# FD : 3
# FDC : 8
# FDCE : 35
# IO Buffers : 106
# IBUF : 34
# FDC : 6
# FDCE : 26
# IO Buffers : 105
# IBUF : 33
# IOBUFE : 32
# OBUF : 37
# OBUFE : 3
@@ -239,13 +241,13 @@ Cell Usage :
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.07 secs
Total CPU time to Xst completion: 7.72 secs
-->
Total memory usage is 290060 kilobytes
Total memory usage is 290008 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 12 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Number of warnings : 13 ( 0 filtered)
Number of infos : 3 ( 0 filtered)