CP working in Z3 and driver update
A fix for int6 is needed for the first proto: Connect SJ1 right with INT6-Pad. But CP and lan are not working with AmiTCP
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@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.13 secs
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Total CPU time to Xst completion: 0.14 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.13 secs
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Total CPU time to Xst completion: 0.14 secs
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--> Reading design: LAN_IDE_CP.prj
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@@ -150,6 +150,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found 1-bit tristate buffer for signal <MTACK>.
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Found 1-bit tristate buffer for signal <DTACK>.
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Found 1-bit tristate buffer for signal <INT_OUT>.
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Found 1-bit tristate buffer for signal <INT_CP_OUT>.
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Found 4-bit tristate buffer for signal <LAN_CFG>.
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Found 1-bit tristate buffer for signal <A<23>>.
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Found 1-bit tristate buffer for signal <A<22>>.
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@@ -167,31 +168,31 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found 1-bit tristate buffer for signal <A<10>>.
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Found 1-bit tristate buffer for signal <A<9>>.
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Found 1-bit tristate buffer for signal <A<8>>.
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 177.
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 178.
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Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE>.
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Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE_CYCLE>.
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Found 1-bit register for signal <AUTOCONFIG_Z2_ACCESS>.
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Found 1-bit register for signal <CONFIG_READY>.
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Found 1-bit register for signal <CP_ACCESS>.
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Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 291.
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Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 292.
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Found 8-bit register for signal <CP_BASEADR>.
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Found 1-bit register for signal <CP_RD_S>.
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Found 1-bit register for signal <CP_WE_QUIRK>.
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Found 1-bit register for signal <CP_WE_S>.
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Found 4-bit register for signal <D_Z2_OUT>.
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Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 636.
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Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 645.
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Found 16-bit register for signal <DQ_DATA>.
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Found 1-bit register for signal <DQ_SWAP>.
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Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 262.
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Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 263.
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Found 1-bit register for signal <IDE_ACCESS>.
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Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 298.
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Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 299.
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Found 8-bit register for signal <IDE_BASEADR>.
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Found 1-bit register for signal <IDE_ENABLE>.
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Found 1-bit register for signal <IDE_R_S>.
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Found 1-bit register for signal <IDE_W_S>.
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Found 14-bit register for signal <LAN_A_INIT>.
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Found 1-bit register for signal <LAN_ACCESS>.
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Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 261.
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Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 262.
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Found 16-bit register for signal <LAN_BASEADR>.
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Found 1-bit register for signal <LAN_CS_RST>.
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Found 16-bit register for signal <LAN_D_INIT>.
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@@ -200,7 +201,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found 1-bit register for signal <LAN_IRQ_OUT>.
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Found 1-bit register for signal <LAN_RD_S>.
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Found 1-bit register for signal <LAN_READY>.
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Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 405.
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Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 406.
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Found 1-bit register for signal <LAN_SM_RST>.
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Found 1-bit register for signal <LAN_WR_RST>.
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Found 1-bit register for signal <LAN_WRH_S>.
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@@ -215,7 +216,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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inferred 74 D-type flip-flop(s).
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inferred 6 Comparator(s).
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inferred 1 Xor(s).
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inferred 57 Tristate(s).
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inferred 58 Tristate(s).
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Unit <LAN_IDE_CP> synthesized.
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@@ -235,8 +236,8 @@ Macro Statistics
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2-bit comparator less : 2
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4-bit comparator less : 1
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8-bit comparator equal : 2
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# Tristates : 27
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1-bit tristate buffer : 25
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# Tristates : 28
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1-bit tristate buffer : 26
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16-bit tristate buffer : 2
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# Xors : 1
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1-bit xor2 : 1
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@@ -394,19 +395,19 @@ Clock Enable : YES
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wysiwyg : NO
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Design Statistics
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# IOs : 116
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# IOs : 117
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Cell Usage :
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# BELS : 1145
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# AND2 : 345
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# AND3 : 41
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# BELS : 1283
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# AND2 : 418
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# AND3 : 44
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# AND4 : 15
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# AND5 : 1
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# AND8 : 4
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# GND : 1
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# INV : 419
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# OR2 : 250
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# OR3 : 17
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# INV : 451
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# OR2 : 277
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# OR3 : 20
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# OR4 : 2
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# XOR2 : 50
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# FlipFlops/Latches : 141
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@@ -415,20 +416,20 @@ Cell Usage :
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# FDCE : 7
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# FDP : 41
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# FDPE : 68
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# IO Buffers : 114
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# IO Buffers : 115
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# IBUF : 24
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# IOBUFE : 48
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# OBUF : 33
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# OBUFE : 9
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# OBUFE : 10
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=========================================================================
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Total REAL time to Xst completion: 18.00 secs
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Total CPU time to Xst completion: 18.70 secs
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Total REAL time to Xst completion: 19.00 secs
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Total CPU time to Xst completion: 19.00 secs
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-->
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Total memory usage is 4534828 kilobytes
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Total memory usage is 4534760 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 48 ( 0 filtered)
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