Byteswap working
This commit is contained in:
MHeinrichs
@@ -30,7 +30,7 @@ NGDBUILD Design Results Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 1
|
||||
|
||||
Total memory usage is 4418744 kilobytes
|
||||
Total memory usage is 4418716 kilobytes
|
||||
|
||||
Writing NGD file "LAN_IDE_CP.ngd" ...
|
||||
Total REAL time to NGDBUILD completion: 5 sec
|
||||
|
||||
@@ -78,3 +78,9 @@ cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -loc on -
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
|
||||
@@ -120,74 +120,79 @@ PARTITION FB1_8 ROM_B_0_OBUF$BUF5
|
||||
PARTITION FB1_10 ROM_B_0_OBUF$BUF4
|
||||
PARTITION FB1_12 ROM_B_0_OBUF$BUF8
|
||||
PARTITION FB1_14 ROM_B_0_OBUF$BUF6 ROM_B_0_OBUF$BUF7
|
||||
PARTITION FB1_17 ROM_B_0_OBUF$BUF3 autoconfig
|
||||
PARTITION FB2_1 LAN_SM_RST A_LAN_4_OBUF A_LAN_7_OBUF LAN_A_INIT<3>
|
||||
A_LAN_6_OBUF N0$BUF5 $OpTx$FX_DC$22 N0$BUF3
|
||||
$OpTx$FX_DC$19 D_6_IOBUFE SHUT_UP D_3_IOBUFE
|
||||
D_9_IOBUFE/D_9_IOBUFE_TRST D_7_IOBUFE D_1_IOBUFE DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
||||
D_8_IOBUFE AUTO_CONFIG_DONE_CYCLE
|
||||
PARTITION FB1_17 ROM_B_0_OBUF$BUF3
|
||||
|
||||
PARTITION FB2_1 Dout1<7> A_LAN_4_OBUF A_LAN_7_OBUF Dout1<3>
|
||||
A_LAN_6_OBUF N0$BUF5 Dout1<0> N0$BUF3
|
||||
Dout1<2> D_6_IOBUFE Dout1<6> D_3_IOBUFE
|
||||
Dout1<5> D_7_IOBUFE D_1_IOBUFE Dout1<4>
|
||||
D_8_IOBUFE Dout1<1>
|
||||
PARTITION FB3_2 ROM_B_0_OBUF$BUF2
|
||||
PARTITION FB3_14 N0$BUF6
|
||||
PARTITION FB3_18 lan_adr
|
||||
PARTITION FB4_1 lan_adr/lan_adr_RSTF D_0_IOBUFE LAN_WR_RST LAN_SM_FSM_FFd4
|
||||
A_LAN_1_OBUF A_LAN_0_OBUF LAN_RST_SM_FSM_FFd1 A_LAN_3_OBUF
|
||||
LAN_D_INIT<8> LAN_D_INIT<1> LAN_CS_RST A_LAN_2_OBUF
|
||||
LAN_A_INIT<6> A_LAN_5_OBUF $OpTx$FX_DC$7 LAN_RST_SM_FSM_FFd3
|
||||
LAN_RST_SM_FSM_FFd2 DQ_DATA<11>
|
||||
|
||||
PARTITION FB4_1 LAN_WR_RST D_0_IOBUFE LAN_RST_SM_FSM_FFd1 LAN_IRQ_D0
|
||||
A_LAN_1_OBUF A_LAN_0_OBUF LAN_D_INIT<8> A_LAN_3_OBUF
|
||||
LAN_D_INIT<1> LAN_CS_RST LAN_A_INIT<6> A_LAN_2_OBUF
|
||||
LAN_WRH_S A_LAN_5_OBUF LAN_RST_SM_FSM_FFd3 LAN_RST_SM_FSM_FFd2
|
||||
LAN_INT_ENABLE LAN_IRQ_OUT
|
||||
PARTITION FB5_2 ROM_B_0_OBUF$BUF11
|
||||
PARTITION FB5_5 ROM_B_0_OBUF Z3_DS/Z3_DS_D2 LAN_SM_FSM_FFd9 LAN_SM_FSM_FFd6
|
||||
LAN_SM_FSM_FFd2 D_2_IOBUFE LAN_SM_FSM_FFd8 D_9_IOBUFE
|
||||
LAN_SM_FSM_FFd7 D_10_IOBUFE D_11_IOBUFE LAN_RD_S
|
||||
D_12_IOBUFE Z3_A_LOW
|
||||
PARTITION FB5_5 ROM_B_0_OBUF
|
||||
PARTITION FB5_7 Z3_ADR_1 Z3_ADR_0 Z3_ADR<9> D_2_IOBUFE
|
||||
Z3_ADR<8> D_9_IOBUFE Z3_ADR<7> D_10_IOBUFE
|
||||
D_11_IOBUFE DQ_DATA<9> D_12_IOBUFE DQ_DATA<1>
|
||||
|
||||
PARTITION FB6_2 N0$BUF4 A_LAN_12_OBUF
|
||||
PARTITION FB6_5 A_LAN_13_OBUF A_LAN_10_OBUF
|
||||
PARTITION FB6_8 A_LAN_11_OBUF
|
||||
PARTITION FB6_10 A_LAN_8_OBUF
|
||||
PARTITION FB6_14 A_LAN_9_OBUF $OpTx$FX_DC$18 LAN_INT_ENABLE LAN_IRQ_OUT
|
||||
DQ_DATA<9>
|
||||
PARTITION FB6_10 A_LAN_8_OBUF N0$BUF7/N0$BUF7_TRST Z3_ADR<6> Z3_ADR<5>
|
||||
A_LAN_9_OBUF Z3_ADR<4> Z3_ADR<3> Z3_ADR<2>
|
||||
Z3_ADR<13>
|
||||
PARTITION FB7_3 D_13_IOBUFE
|
||||
PARTITION FB7_5 D_14_IOBUFE
|
||||
PARTITION FB7_12 D_15_IOBUFE
|
||||
PARTITION FB7_15 LAN_IRQ_D0 DQ_DATA<14> DQ_DATA<13> DQ_DATA<12>
|
||||
PARTITION FB7_15 lan_adr Z3_ADR<12> Z3_ADR<11> dq_swap
|
||||
|
||||
PARTITION FB8_2 DQ_12_IOBUFE DQ_14_IOBUFE
|
||||
PARTITION FB8_5 LAN_WRH_OBUF
|
||||
PARTITION FB8_8 LAN_CS_OBUF
|
||||
PARTITION FB8_10 LAN_RD_OBUF
|
||||
PARTITION FB8_13 $OpTx$FX_DC$14 LAN_SM_FSM_FFd5 LAN_SM_FSM_FFd1 lan_rdy
|
||||
Z3_DATA<16> LAN_SM_FSM_FFd3
|
||||
PARTITION FB9_11 Z3_DATA<0> Z3_ADR<13> Z3_ADR<12> Z3_DATA<1>
|
||||
DQ_DATA<8> DQ_DATA<7> Z3_DATA<2> DQ_DATA<6>
|
||||
PARTITION FB8_5 LAN_WRH_OBUF lan_adr/lan_adr_RSTF Z3_DS/Z3_DS_D2 LAN_CS_OBUF
|
||||
$OpTx$FX_DC$5 LAN_RD_OBUF $OpTx$FX_DC$23 LAN_SM_FSM_FFd6
|
||||
LAN_SM_FSM_FFd4 LAN_SM_FSM_FFd2 LAN_SM_FSM_FFd1 D_9_IOBUFE/D_9_IOBUFE_TRST
|
||||
LAN_WRL_S LAN_SM_FSM_FFd7
|
||||
PARTITION FB9_1 DQ_DATA<4> EXP22_
|
||||
PARTITION FB9_11 Z3_DATA<0> EXP23_ DQ_DATA<5> Z3_DATA<1>
|
||||
EXP24_ DQ_DATA<13> Z3_DATA<2> DQ_DATA<12>
|
||||
|
||||
PARTITION FB10_1 Dout1<7> DQ_1_IOBUFE DQ_0_IOBUFE Dout1<3>
|
||||
DQ_3_IOBUFE DQ_2_IOBUFE Dout1<0> DQ_5_IOBUFE
|
||||
Dout1<2> DQ_4_IOBUFE DQ_7_IOBUFE DQ_6_IOBUFE
|
||||
Dout1<6> DQ_8_IOBUFE Dout1<5> Dout1<4>
|
||||
DQ_10_IOBUFE Dout1<1>
|
||||
PARTITION FB11_1 Z3_DATA<31> Z3_DATA<30> Z3_DATA<3> Z3_DATA<29>
|
||||
Z3_DATA<4> Z3_DATA<28> Z3_DATA<23> Z3_DATA<22>
|
||||
Z3_DATA<21> Z3_DATA<5> Z3_DATA<6> ROM_B_0_OBUF$BUF1
|
||||
Z3_DATA<20> ROM_B_0_OBUF$BUF0 Z3_DATA<19> Z3_DATA<18>
|
||||
ROM_B_0_OBUF$BUF9 Z3_DATA<17>
|
||||
PARTITION FB10_1 EXP25_ DQ_1_IOBUFE DQ_0_IOBUFE
|
||||
PARTITION FB10_5 DQ_3_IOBUFE DQ_2_IOBUFE LAN_A_INIT<3> DQ_5_IOBUFE
|
||||
$OpTx$FX_DC$6 DQ_4_IOBUFE DQ_7_IOBUFE DQ_6_IOBUFE
|
||||
DQ_DATA<8> DQ_8_IOBUFE DQ_DATA<2> DQ_DATA<10>
|
||||
DQ_10_IOBUFE DQ_DATA<0>
|
||||
PARTITION FB11_1 $OpTx$FX_DC$16 lan_rdy Z3_DATA<3> LAN_SM_FSM_FFd8
|
||||
Z3_DATA<4> LAN_SM_FSM_FFd3 LAN_SM_FSM_FFd10 LAN_RD_S
|
||||
Z3_DATA<30> Z3_DATA<5> Z3_DATA<6> ROM_B_0_OBUF$BUF1
|
||||
Z3_DATA<29> ROM_B_0_OBUF$BUF0 Z3_DATA<22> Z3_DATA<21>
|
||||
ROM_B_0_OBUF$BUF9 Z3_A_LOW
|
||||
PARTITION FB12_2 N0$BUF2
|
||||
PARTITION FB12_5 DQ_15_IOBUFE $OpTx$FX_DC$4 Z3_ADR_1 DQ_13_IOBUFE
|
||||
Z3_ADR_0 DQ_11_IOBUFE Z3_ADR<6> DQ_9_IOBUFE
|
||||
Z3_ADR<5> Z3_ADR<4> Z3_ADR<3> Z3_ADR<2>
|
||||
LAN_WRL_S LAN_WRH_S
|
||||
PARTITION FB13_2 ROM_B_0_OBUF$BUF10
|
||||
PARTITION FB12_5 DQ_15_IOBUFE
|
||||
PARTITION FB12_8 DQ_13_IOBUFE
|
||||
PARTITION FB12_10 DQ_11_IOBUFE
|
||||
PARTITION FB12_12 DQ_9_IOBUFE
|
||||
PARTITION FB12_17 autoconfig Z3_ADR<10>
|
||||
PARTITION FB13_1 LAN_SM_FSM_FFd5 ROM_B_0_OBUF$BUF10
|
||||
PARTITION FB13_8 Z3_DATA<7>
|
||||
PARTITION FB13_13 Z3_ADR<8> LAN_WRL_OBUF Z3_ADR<7> DQ_DATA<2>
|
||||
DQ_DATA<1> DQ_DATA<15>
|
||||
PARTITION FB13_14 LAN_WRL_OBUF DQ_DATA<7> DQ_DATA<6> DQ_DATA<15>
|
||||
DQ_DATA<14>
|
||||
PARTITION FB14_3 N0$BUF0
|
||||
PARTITION FB14_11 CFOUT_OBUF
|
||||
PARTITION FB14_14 SLAVE_OBUF N0
|
||||
PARTITION FB14_18 N0$BUF7/N0$BUF7_TRST
|
||||
PARTITION FB15_9 Z3_ADR<9> Z3_ADR<11> Z3_ADR<10> N0$BUF7
|
||||
DQ_DATA<5> Z3_DATA<15> Z3_DATA<14> DQ_DATA<4>
|
||||
Z3_DATA<13> DQ_DATA<3>
|
||||
PARTITION FB16_1 BUF_LAN_SM_FSM_FFd9 Z3_DATA<12> Z3_DATA<11> $OpTx$FX_SC$29
|
||||
$OpTx$FX_DC$25 Z3_DATA<10> LAN_SM_FSM_FFd12 Z3_DATA<9>
|
||||
LAN_SM_FSM_FFd11 N0$BUF1 Z3_DATA<8> Z3_DATA<27>
|
||||
Z3_DATA<26> Z3_DATA<25> Z3_DATA<24> LAN_SM_FSM_FFd10
|
||||
DQ_DATA<10> DQ_DATA<0>
|
||||
|
||||
PARTITION FB15_1 DQ_DATA<11> DQ_DATA<3> Z3_DATA<23> Z3_DATA<31>
|
||||
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST LAN_SM_FSM_FFd11 LAN_SM_FSM_FFd12 LAN_SM_FSM_FFd9
|
||||
$OpTx$FX_DC$24 $OpTx$FX_DC$27 $OpTx$FX_DC$30 N0$BUF7
|
||||
$OpTx$FX_SC$34 Z3_DATA<15> Z3_DATA<14> BUF_LAN_SM_FSM_FFd9
|
||||
Z3_DATA<13> LAN_SM_RST
|
||||
PARTITION FB16_1 SHUT_UP Z3_DATA<12> Z3_DATA<11> AUTO_CONFIG_DONE_CYCLE
|
||||
Z3_DATA<28> Z3_DATA<10> Z3_DATA<27> Z3_DATA<9>
|
||||
Z3_DATA<26> N0$BUF1 Z3_DATA<8> Z3_DATA<25>
|
||||
Z3_DATA<24> Z3_DATA<20> Z3_DATA<19> Z3_DATA<18>
|
||||
Z3_DATA<17> Z3_DATA<16>
|
||||
|
||||
|
||||
+926
-926
File diff suppressed because it is too large
Load Diff
+984
-744
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@@ -1,7 +1,7 @@
|
||||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
12-17-2018 11:55PM
|
||||
12-18-2018 0:00AM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
|
||||
|
||||
+908
-756
File diff suppressed because it is too large
Load Diff
@@ -89,8 +89,6 @@ Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <beh
|
||||
* HDL Analysis *
|
||||
=========================================================================
|
||||
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
|
||||
WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" line 291: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
|
||||
<LAN_SM_RST>
|
||||
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
|
||||
|
||||
|
||||
@@ -116,7 +114,6 @@ WARNING:Xst:647 - Input <CP_IRQ> is never used. This port will be preserved and
|
||||
WARNING:Xst:2565 - Inout <A<1>> is never assigned.
|
||||
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <C1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:646 - Signal <dq_swap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
WARNING:Xst:646 - Signal <LAN_BASEADR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
|
||||
Found finite state machine <FSM_0> for signal <LAN_SM>.
|
||||
@@ -177,6 +174,8 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
|
||||
Found 1-bit register for signal <autoconfig>.
|
||||
Found 8-bit register for signal <Dout1>.
|
||||
Found 16-bit register for signal <DQ_DATA>.
|
||||
Found 1-bit register for signal <dq_swap>.
|
||||
Found 2-bit comparator less for signal <dq_swap$cmp_lt0000> created at line 248.
|
||||
Found 14-bit register for signal <LAN_A_INIT>.
|
||||
Found 1-bit register for signal <lan_adr>.
|
||||
Found 1-bit register for signal <LAN_CS_RST>.
|
||||
@@ -197,7 +196,8 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
|
||||
Summary:
|
||||
inferred 2 Finite State Machine(s).
|
||||
inferred 1 ROM(s).
|
||||
inferred 47 D-type flip-flop(s).
|
||||
inferred 48 D-type flip-flop(s).
|
||||
inferred 1 Comparator(s).
|
||||
inferred 57 Tristate(s).
|
||||
Unit <LAN_IDE_CP> synthesized.
|
||||
|
||||
@@ -208,11 +208,13 @@ HDL Synthesis Report
|
||||
Macro Statistics
|
||||
# ROMs : 1
|
||||
16x8-bit ROM : 1
|
||||
# Registers : 53
|
||||
1-bit register : 48
|
||||
# Registers : 54
|
||||
1-bit register : 49
|
||||
14-bit register : 2
|
||||
16-bit register : 2
|
||||
8-bit register : 1
|
||||
# Comparators : 1
|
||||
2-bit comparator less : 1
|
||||
# Tristates : 27
|
||||
1-bit tristate buffer : 25
|
||||
16-bit tristate buffer : 2
|
||||
@@ -286,8 +288,8 @@ Macro Statistics
|
||||
# FSMs : 2
|
||||
# ROMs : 1
|
||||
16x8-bit ROM : 1
|
||||
# Registers : 47
|
||||
Flip-Flops : 47
|
||||
# Registers : 48
|
||||
Flip-Flops : 48
|
||||
|
||||
=========================================================================
|
||||
|
||||
@@ -378,22 +380,22 @@ Design Statistics
|
||||
# IOs : 116
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 599
|
||||
# AND2 : 193
|
||||
# AND3 : 18
|
||||
# BELS : 779
|
||||
# AND2 : 258
|
||||
# AND3 : 34
|
||||
# AND4 : 7
|
||||
# AND8 : 3
|
||||
# GND : 1
|
||||
# INV : 189
|
||||
# OR2 : 146
|
||||
# INV : 239
|
||||
# OR2 : 195
|
||||
# OR3 : 22
|
||||
# OR4 : 2
|
||||
# OR8 : 16
|
||||
# VCC : 1
|
||||
# XOR2 : 1
|
||||
# FlipFlops/Latches : 105
|
||||
# FlipFlops/Latches : 106
|
||||
# FD : 1
|
||||
# FDC : 25
|
||||
# FDC : 26
|
||||
# FDCE : 3
|
||||
# FDP : 42
|
||||
# FDPE : 34
|
||||
@@ -406,13 +408,13 @@ Cell Usage :
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 8.00 secs
|
||||
Total CPU time to Xst completion: 8.40 secs
|
||||
Total CPU time to Xst completion: 8.29 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 4534752 kilobytes
|
||||
Total memory usage is 4534748 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 54 ( 0 filtered)
|
||||
Number of warnings : 52 ( 0 filtered)
|
||||
Number of infos : 10 ( 0 filtered)
|
||||
|
||||
|
||||
+174
-94
@@ -1,117 +1,157 @@
|
||||
TS_CLK_EXT:FROM:DQ_DATA<8>.Q:TO:Z3_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<8>.Q:TO:Z3_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<0>.Q:TO:Z3_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<0>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<0>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<2>.Q:TO:Z3_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<10>.Q:TO:Z3_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<8>.Q:TO:Z3_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<10>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<10>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<3>.Q:TO:Z3_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<11>.Q:TO:Z3_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<8>.Q:TO:Z3_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<11>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<11>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<4>.Q:TO:Z3_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<1>.Q:TO:Z3_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<12>.Q:TO:Z3_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<12>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<12>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<5>.Q:TO:Z3_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<13>.Q:TO:Z3_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<13>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<13>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<6>.Q:TO:Z3_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<14>.Q:TO:Z3_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<14>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<14>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<7>.Q:TO:Z3_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<15>.Q:TO:Z3_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<15>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<15>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<1>.Q:TO:Z3_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<9>.Q:TO:Z3_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<1>.Q:TO:Z3_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<1>.Q:TO:Z3_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<1>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<1>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<2>.Q:TO:Z3_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<10>.Q:TO:Z3_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<8>.Q:TO:Z3_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<2>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<2>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<3>.Q:TO:Z3_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<11>.Q:TO:Z3_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<8>.Q:TO:Z3_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<3>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<3>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<4>.Q:TO:Z3_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<1>.Q:TO:Z3_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<12>.Q:TO:Z3_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<4>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<4>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<5>.Q:TO:Z3_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<13>.Q:TO:Z3_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<5>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<5>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<6>.Q:TO:Z3_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<14>.Q:TO:Z3_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<6>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<6>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<7>.Q:TO:Z3_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<15>.Q:TO:Z3_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<7>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<7>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<8>.Q:TO:Z3_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<8>.Q:TO:Z3_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<0>.Q:TO:Z3_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<8>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<8>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<9>.Q:TO:Z3_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<1>.Q:TO:Z3_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<1>.Q:TO:Z3_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<9>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:Z3_DATA<9>.CE:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<7>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_INT_ENABLE.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:AUTO_CONFIG_DONE_CYCLE.Q:TO:AUTO_CONFIG_DONE_CYCLE.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<30>.Q:TO:LAN_IRQ_OUT.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<6>.Q:TO:LAN_IRQ_OUT.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<30>.Q:TO:LAN_IRQ_OUT.D:400
|
||||
TS_CLK_EXT:FROM:LAN_INT_ENABLE.Q:TO:LAN_IRQ_OUT.D:400
|
||||
TS_CLK_EXT:FROM:LAN_IRQ_D0.Q:TO:LAN_IRQ_OUT.D:400
|
||||
TS_CLK_EXT:FROM:LAN_IRQ_OUT.Q:TO:LAN_IRQ_OUT.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<8>.Q:TO:Z3_DATA<16>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<8>.Q:TO:Z3_DATA<16>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<0>.Q:TO:Z3_DATA<16>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<16>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<16>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<1>.Q:TO:Z3_DATA<17>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<9>.Q:TO:Z3_DATA<17>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<1>.Q:TO:Z3_DATA<17>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<1>.Q:TO:Z3_DATA<17>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<17>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<17>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<2>.Q:TO:Z3_DATA<18>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<10>.Q:TO:Z3_DATA<18>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<8>.Q:TO:Z3_DATA<18>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<18>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<18>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<3>.Q:TO:Z3_DATA<19>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<11>.Q:TO:Z3_DATA<19>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<8>.Q:TO:Z3_DATA<19>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<19>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<19>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<4>.Q:TO:Z3_DATA<20>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<1>.Q:TO:Z3_DATA<20>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<12>.Q:TO:Z3_DATA<20>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<20>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<20>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<5>.Q:TO:Z3_DATA<21>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<13>.Q:TO:Z3_DATA<21>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<21>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<21>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<6>.Q:TO:Z3_DATA<22>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<14>.Q:TO:Z3_DATA<22>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<22>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<22>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<7>.Q:TO:Z3_DATA<23>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<15>.Q:TO:Z3_DATA<23>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<23>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<23>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<8>.Q:TO:Z3_DATA<24>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<8>.Q:TO:Z3_DATA<24>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<0>.Q:TO:Z3_DATA<24>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<24>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<24>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<9>.Q:TO:Z3_DATA<25>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<1>.Q:TO:Z3_DATA<25>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<1>.Q:TO:Z3_DATA<25>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<25>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<25>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<2>.Q:TO:Z3_DATA<26>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<10>.Q:TO:Z3_DATA<26>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<8>.Q:TO:Z3_DATA<26>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<26>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<26>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<3>.Q:TO:Z3_DATA<27>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<11>.Q:TO:Z3_DATA<27>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<8>.Q:TO:Z3_DATA<27>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<27>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<27>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<4>.Q:TO:Z3_DATA<28>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_D_INIT<1>.Q:TO:Z3_DATA<28>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<12>.Q:TO:Z3_DATA<28>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<28>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<28>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<5>.Q:TO:Z3_DATA<29>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<13>.Q:TO:Z3_DATA<29>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<29>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<29>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<6>.Q:TO:Z3_DATA<30>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<14>.Q:TO:Z3_DATA<30>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<30>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<30>.CE:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<7>.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<15>.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<31>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_DATA<31>.CE:400
|
||||
@@ -120,8 +160,8 @@ TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:LAN_SM_FSM_FFd12.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:LAN_SM_FSM_FFd7.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:LAN_SM_FSM_FFd7.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:LAN_SM_FSM_FFd7.RSTF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:LAN_SM_FSM_FFd5.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:LAN_SM_FSM_FFd5.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:LAN_SM_FSM_FFd5.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:LAN_SM_FSM_FFd5.RSTF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:LAN_SM_FSM_FFd3.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:LAN_SM_FSM_FFd3.D:400
|
||||
@@ -155,269 +195,309 @@ TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_RST_SM_FSM_FFd3.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_RST_SM_FSM_FFd3.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_D_INIT<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_D_INIT<8>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<0>.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<16>.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<0>.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<0>.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<24>.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<16>.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<0>.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<8>.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<0>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<10>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<26>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<2>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<10>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<18>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<2>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<26>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<10>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<2>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<10>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<11>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<27>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<3>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<11>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<19>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<3>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<27>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<11>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<3>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<11>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<12>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<28>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<4>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<12>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<20>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<4>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<28>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<12>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<4>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<12>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<13>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<29>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<5>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<13>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<21>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<5>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<29>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<13>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<5>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<13>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<14>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<30>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<6>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<14>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<22>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<6>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<30>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<14>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<6>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<14>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<15>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<7>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<15>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<23>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<7>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<15>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<7>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<15>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<1>.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<17>.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<1>.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<1>.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<25>.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<17>.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<1>.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<9>.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<1>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<2>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<18>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<2>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<18>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<2>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<26>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<10>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<2>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<2>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<3>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<19>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<3>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<19>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<3>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<27>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<11>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<3>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<3>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<4>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<20>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<4>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<20>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<4>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<28>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<12>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<4>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<4>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<5>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<21>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<5>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<21>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<5>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<29>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<13>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<5>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<5>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<6>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<22>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<6>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<22>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<6>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<30>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<14>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<6>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<6>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<7>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<23>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<7>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<23>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<7>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<15>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<7>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<7>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<8>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<24>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<0>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<8>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<0>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<24>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<16>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<0>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<8>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<8>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<9>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<25>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<1>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<9>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd10.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd11.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd8.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd9.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd6.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd12.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Dout1<1>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<25>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<17>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<1>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<9>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<9>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_WR_RST.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_WR_RST.D:400
|
||||
@@ -446,7 +526,7 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:Z3_A_LOW.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_A_LOW.RSTF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:lan_rdy.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd7.Q:TO:lan_rdy.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:lan_rdy.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:lan_rdy.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd5.Q:TO:lan_rdy.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:lan_rdy.RSTF:400
|
||||
TS_CLK_EXT:FROM:AUTO_CONFIG_DONE_CYCLE.Q:TO:CFOUT_OBUF.D:400
|
||||
|
||||
@@ -288,7 +288,7 @@ begin
|
||||
end process lan_rst_gen;
|
||||
|
||||
--lan signal generation: all Signals are HIGH active!
|
||||
lan_rw_gen: process (CLK_EXT,FCS,reset)
|
||||
lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
|
||||
begin
|
||||
if(LAN_SM_RST ='1' ) then
|
||||
LAN_SM <=nop;
|
||||
@@ -314,17 +314,17 @@ begin
|
||||
-- this is a quite complex thing for a cpld
|
||||
-- so I have to move this out of the cycle start condition and prepare it for every loop
|
||||
if(UDS='0' or LDS='0')then
|
||||
--if(dq_swap='0') then
|
||||
if(dq_swap='0') then
|
||||
DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
|
||||
--else
|
||||
-- DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
|
||||
--end if;
|
||||
else
|
||||
--if(dq_swap='0') then
|
||||
DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
|
||||
end if;
|
||||
else
|
||||
if(dq_swap='0') then
|
||||
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
|
||||
--else
|
||||
-- DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
|
||||
--end if;
|
||||
else
|
||||
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
|
||||
end if;
|
||||
end if;
|
||||
if(lan_adr = '1' and Z3_DS = '0' and Z3_ADR(15) = '0' )then --cycle start!
|
||||
|
||||
@@ -356,11 +356,11 @@ begin
|
||||
LAN_SM<=end_read_upper;
|
||||
when end_read_upper=>
|
||||
--fetch data
|
||||
--if(dq_swap='0') then
|
||||
if(dq_swap='0') then
|
||||
Z3_DATA(31 downto 16) <= DQ;
|
||||
--else
|
||||
-- Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
|
||||
--end if;
|
||||
else
|
||||
Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
|
||||
end if;
|
||||
if(DS1='1' and DS0='1')then -- no lower half
|
||||
lan_rdy <='1';
|
||||
LAN_SM <= end_read_upper; -- stay here until cylce end
|
||||
@@ -378,11 +378,11 @@ begin
|
||||
LAN_SM<=end_read_lower;
|
||||
when end_read_lower=>
|
||||
--fetch data
|
||||
--if(dq_swap='0') then
|
||||
if(dq_swap='0') then
|
||||
Z3_DATA(15 downto 0) <= DQ;
|
||||
--else
|
||||
-- Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
|
||||
--end if;
|
||||
else
|
||||
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
|
||||
end if;
|
||||
lan_rdy <='1';
|
||||
LAN_SM<=end_read_lower; -- stay here until cylce end
|
||||
when start_write_upper=>
|
||||
@@ -394,11 +394,11 @@ begin
|
||||
LAN_SM<=end_write_upper;
|
||||
when end_write_upper=>
|
||||
-- prepare the data for write
|
||||
--if(dq_swap='0') then
|
||||
if(dq_swap='0') then
|
||||
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
|
||||
--else
|
||||
-- DQ_DATA(15 downto 0) <= Z3_DATA_IN(7 downto 0) & Z3_DATA_IN(15 downto 8);
|
||||
--end if;
|
||||
else
|
||||
DQ_DATA(15 downto 0) <= Z3_DATA_IN(7 downto 0) & Z3_DATA_IN(15 downto 8);
|
||||
end if;
|
||||
|
||||
if(DS1='1' and DS0='1')then -- no lower half
|
||||
lan_rdy <='1';
|
||||
|
||||
+5407
-4473
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@@ -6,95 +6,127 @@
|
||||
********** Mapped Logic **********
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
$OpTx$FX_DC$14 <= (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5 AND
|
||||
$OpTx$FX_DC$16 <= (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd9 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd11 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd4);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
$OpTx$FX_DC$18 <= (DS1 AND DS0);
|
||||
$OpTx$FX_DC$23 <= (DS1 AND DS0);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
$OpTx$FX_DC$19 <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
$OpTx$FX_DC$24 <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
$OpTx$FX_DC$22 <= (RESET AND NOT FCS);
|
||||
$OpTx$FX_DC$27 <= (RESET AND NOT FCS);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
$OpTx$FX_DC$25 <= (NOT RW AND lan_adr AND Z3_ADR(13) AND NOT Z3_DS/Z3_DS_D2);
|
||||
$OpTx$FX_DC$30 <= (NOT RW AND lan_adr AND Z3_ADR(13) AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
$OpTx$FX_DC$4 <= (UDS AND LDS);
|
||||
$OpTx$FX_DC$5 <= (UDS AND LDS);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
$OpTx$FX_DC$7 <= ((LAN_SM_FSM_FFd3)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND $OpTx$FX_DC$4));
|
||||
$OpTx$FX_DC$6 <= ((LAN_SM_FSM_FFd3)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
$OpTx$FX_SC$29 <= (LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
|
||||
$OpTx$FX_SC$34 <= (LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
|
||||
<br/> NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A8: FDCPE port map (A_I(8),DQ(0).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A8: FDCPE port map (A_I(8),A(8),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(8) <= ((dq_swap AND DQ(8).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(0).PIN));
|
||||
<br/> A(8) <= A_I(8) when A_OE(8) = '1' else 'Z';
|
||||
<br/> A_OE(8) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A9: FDCPE port map (A_I(9),DQ(1).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A9: FDCPE port map (A_I(9),A(9),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(9) <= ((dq_swap AND DQ(9).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(1).PIN));
|
||||
<br/> A(9) <= A_I(9) when A_OE(9) = '1' else 'Z';
|
||||
<br/> A_OE(9) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A10: FDCPE port map (A_I(10),DQ(2).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A10: FDCPE port map (A_I(10),A(10),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(10) <= ((dq_swap AND DQ(10).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(2).PIN));
|
||||
<br/> A(10) <= A_I(10) when A_OE(10) = '1' else 'Z';
|
||||
<br/> A_OE(10) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A11: FDCPE port map (A_I(11),DQ(3).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A11: FDCPE port map (A_I(11),A(11),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(11) <= ((dq_swap AND DQ(11).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(3).PIN));
|
||||
<br/> A(11) <= A_I(11) when A_OE(11) = '1' else 'Z';
|
||||
<br/> A_OE(11) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A12: FDCPE port map (A_I(12),DQ(4).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A12: FDCPE port map (A_I(12),A(12),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(12) <= ((dq_swap AND DQ(12).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(4).PIN));
|
||||
<br/> A(12) <= A_I(12) when A_OE(12) = '1' else 'Z';
|
||||
<br/> A_OE(12) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A13: FDCPE port map (A_I(13),DQ(5).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A13: FDCPE port map (A_I(13),A(13),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(13) <= ((dq_swap AND DQ(13).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(5).PIN));
|
||||
<br/> A(13) <= A_I(13) when A_OE(13) = '1' else 'Z';
|
||||
<br/> A_OE(13) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A14: FDCPE port map (A_I(14),DQ(6).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A14: FDCPE port map (A_I(14),A(14),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(14) <= ((dq_swap AND DQ(14).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(6).PIN));
|
||||
<br/> A(14) <= A_I(14) when A_OE(14) = '1' else 'Z';
|
||||
<br/> A_OE(14) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A15: FDCPE port map (A_I(15),DQ(7).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A15: FDCPE port map (A_I(15),A(15),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(15) <= ((dq_swap AND DQ(15).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(7).PIN));
|
||||
<br/> A(15) <= A_I(15) when A_OE(15) = '1' else 'Z';
|
||||
<br/> A_OE(15) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A16: FDCPE port map (A_I(16),DQ(8).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A16: FDCPE port map (A_I(16),A(16),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(16) <= ((dq_swap AND DQ(0).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(8).PIN));
|
||||
<br/> A(16) <= A_I(16) when A_OE(16) = '1' else 'Z';
|
||||
<br/> A_OE(16) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A17: FDCPE port map (A_I(17),DQ(9).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A17: FDCPE port map (A_I(17),A(17),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(17) <= ((dq_swap AND DQ(1).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(9).PIN));
|
||||
<br/> A(17) <= A_I(17) when A_OE(17) = '1' else 'Z';
|
||||
<br/> A_OE(17) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A18: FDCPE port map (A_I(18),DQ(10).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A18: FDCPE port map (A_I(18),A(18),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(18) <= ((dq_swap AND DQ(2).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(10).PIN));
|
||||
<br/> A(18) <= A_I(18) when A_OE(18) = '1' else 'Z';
|
||||
<br/> A_OE(18) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A19: FDCPE port map (A_I(19),DQ(11).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A19: FDCPE port map (A_I(19),A(19),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(19) <= ((dq_swap AND DQ(3).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(11).PIN));
|
||||
<br/> A(19) <= A_I(19) when A_OE(19) = '1' else 'Z';
|
||||
<br/> A_OE(19) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A20: FDCPE port map (A_I(20),DQ(12).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A20: FDCPE port map (A_I(20),A(20),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(20) <= ((dq_swap AND DQ(4).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(12).PIN));
|
||||
<br/> A(20) <= A_I(20) when A_OE(20) = '1' else 'Z';
|
||||
<br/> A_OE(20) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A21: FDCPE port map (A_I(21),DQ(13).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A21: FDCPE port map (A_I(21),A(21),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(21) <= ((dq_swap AND DQ(5).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(13).PIN));
|
||||
<br/> A(21) <= A_I(21) when A_OE(21) = '1' else 'Z';
|
||||
<br/> A_OE(21) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A22: FDCPE port map (A_I(22),DQ(14).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A22: FDCPE port map (A_I(22),A(22),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(22) <= ((dq_swap AND DQ(6).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(14).PIN));
|
||||
<br/> A(22) <= A_I(22) when A_OE(22) = '1' else 'Z';
|
||||
<br/> A_OE(22) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_A23: FDCPE port map (A_I(23),DQ(15).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
FDCPE_A23: FDCPE port map (A_I(23),A(23),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
|
||||
<br/> A(23) <= ((dq_swap AND DQ(7).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(15).PIN));
|
||||
<br/> A(23) <= A_I(23) when A_OE(23) = '1' else 'Z';
|
||||
<br/> A_OE(23) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
@@ -149,7 +181,7 @@ A_LAN(13) <= NOT ((RESET AND NOT Z3_ADR(12)));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
BUF_LAN_SM_FSM_FFd9 <= (NOT RW AND LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
|
||||
<br/> NOT $OpTx$FX_DC$4);
|
||||
<br/> NOT $OpTx$FX_DC$5);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_CFOUT: FDCPE port map (CFOUT,CFOUT_D,CLK_EXT,'0',NOT RESET,FCS);
|
||||
<br/> CFOUT_D <= (NOT AUTO_CONFIG_DONE_CYCLE AND AUTOBOOT_OFF);
|
||||
@@ -164,90 +196,90 @@ CP_RD <= '1';
|
||||
CP_WE <= '1';
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(0) <= NOT ((NOT Z3_DATA(16) AND $OpTx$FX_DC$19));
|
||||
D_I(0) <= NOT ((NOT Z3_DATA(16) AND $OpTx$FX_DC$24));
|
||||
<br/> D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
|
||||
<br/> D_OE(0) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(1) <= NOT ((NOT Z3_DATA(17) AND $OpTx$FX_DC$19));
|
||||
D_I(1) <= NOT ((NOT Z3_DATA(17) AND $OpTx$FX_DC$24));
|
||||
<br/> D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
|
||||
<br/> D_OE(1) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(2) <= NOT ((NOT Z3_DATA(18) AND $OpTx$FX_DC$19));
|
||||
D_I(2) <= NOT ((NOT Z3_DATA(18) AND $OpTx$FX_DC$24));
|
||||
<br/> D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
|
||||
<br/> D_OE(2) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(3) <= NOT ((NOT Z3_DATA(19) AND $OpTx$FX_DC$19));
|
||||
D_I(3) <= NOT ((NOT Z3_DATA(19) AND $OpTx$FX_DC$24));
|
||||
<br/> D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
|
||||
<br/> D_OE(3) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(4) <= NOT ((NOT Z3_DATA(20) AND $OpTx$FX_DC$19));
|
||||
D_I(4) <= NOT ((NOT Z3_DATA(20) AND $OpTx$FX_DC$24));
|
||||
<br/> D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
|
||||
<br/> D_OE(4) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(5) <= NOT ((NOT Z3_DATA(21) AND $OpTx$FX_DC$19));
|
||||
D_I(5) <= NOT ((NOT Z3_DATA(21) AND $OpTx$FX_DC$24));
|
||||
<br/> D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
|
||||
<br/> D_OE(5) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(6) <= NOT ((NOT Z3_DATA(22) AND $OpTx$FX_DC$19));
|
||||
D_I(6) <= NOT ((NOT Z3_DATA(22) AND $OpTx$FX_DC$24));
|
||||
<br/> D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
|
||||
<br/> D_OE(6) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(7) <= NOT ((NOT Z3_DATA(23) AND $OpTx$FX_DC$19));
|
||||
D_I(7) <= NOT ((NOT Z3_DATA(23) AND $OpTx$FX_DC$24));
|
||||
<br/> D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
|
||||
<br/> D_OE(7) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(8) <= ((Z3_DATA(24) AND $OpTx$FX_DC$19)
|
||||
<br/> OR (Dout1(0) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(8) <= ((Z3_DATA(24) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(0) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
|
||||
<br/> D_OE(8) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(9) <= ((Z3_DATA(25) AND $OpTx$FX_DC$19)
|
||||
<br/> OR (Dout1(1) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(9) <= ((Z3_DATA(25) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(1) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
|
||||
<br/> D_OE(9) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(10) <= ((Z3_DATA(26) AND $OpTx$FX_DC$19)
|
||||
<br/> OR (Dout1(2) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(10) <= ((Z3_DATA(26) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(2) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
|
||||
<br/> D_OE(10) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(11) <= ((Z3_DATA(27) AND $OpTx$FX_DC$19)
|
||||
<br/> OR (Dout1(3) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(11) <= ((Z3_DATA(27) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(3) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
|
||||
<br/> D_OE(11) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(12) <= ((Z3_DATA(28) AND $OpTx$FX_DC$19)
|
||||
<br/> OR (Dout1(4) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(12) <= ((Z3_DATA(28) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(4) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
|
||||
<br/> D_OE(12) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(13) <= ((Z3_DATA(29) AND $OpTx$FX_DC$19)
|
||||
<br/> OR (Dout1(5) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(13) <= ((Z3_DATA(29) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(5) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
|
||||
<br/> D_OE(13) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(14) <= ((Z3_DATA(30) AND $OpTx$FX_DC$19)
|
||||
<br/> OR (Dout1(6) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(14) <= ((Z3_DATA(30) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(6) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
|
||||
<br/> D_OE(14) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(15) <= ((Z3_DATA(31) AND $OpTx$FX_DC$19)
|
||||
<br/> OR (Dout1(7) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(15) <= ((Z3_DATA(31) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(7) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
|
||||
<br/> D_OE(15) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
@@ -339,87 +371,151 @@ DQ_I(15) <= (RESET AND DQ_DATA(15));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST <= ((NOT RESET)
|
||||
<br/> OR (NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2 AND NOT $OpTx$FX_DC$19));
|
||||
<br/> OR (NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2 AND NOT $OpTx$FX_DC$24));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA0: FDCPE port map (DQ_DATA(0),DQ_DATA_D(0),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(0) <= ((A(8).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(0) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(0).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(0) <= ((D(8).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(0) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(16).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(8).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(0).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA1: FDCPE port map (DQ_DATA(1),DQ_DATA_D(1),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(1) <= ((DQ_DATA(1) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (A(9).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(1).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(1) <= ((D(9).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(1) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(17).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(9).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(1).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA2: FDCPE port map (DQ_DATA(2),DQ_DATA_D(2),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(2) <= ((DQ_DATA(2) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (A(10).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(2).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(2) <= ((D(10).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(2) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(18).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(10).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(2).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA3: FDCPE port map (DQ_DATA(3),DQ_DATA_D(3),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(3) <= ((DQ_DATA(3) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (A(11).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(3).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(3) <= ((D(11).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(3) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(19).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(11).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(3).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA4: FDCPE port map (DQ_DATA(4),DQ_DATA_D(4),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(4) <= ((DQ_DATA(4) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (A(12).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(4).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(4) <= ((D(12).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(4).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(4) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(20).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(12).PIN AND $OpTx$FX_DC$6));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA5: FDCPE port map (DQ_DATA(5),DQ_DATA_D(5),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(5) <= ((DQ_DATA(5) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (A(13).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(5).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(5) <= ((D(13).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(5) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(21).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(13).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(5).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA6: FDCPE port map (DQ_DATA(6),DQ_DATA_D(6),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(6) <= ((DQ_DATA(6) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (A(14).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(6).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(6) <= ((D(14).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(6) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(22).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(14).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(6).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA7: FDCPE port map (DQ_DATA(7),DQ_DATA_D(7),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(7) <= ((A(15).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(7) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(7).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(7) <= ((D(15).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(7).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(7) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(23).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(15).PIN AND $OpTx$FX_DC$6));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA8: FDCPE port map (DQ_DATA(8),DQ_DATA_D(8),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(8) <= ((A(16).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(8) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(8).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(8) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(0).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(8) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(16).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(8).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(8).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA9: FDCPE port map (DQ_DATA(9),DQ_DATA_D(9),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(9) <= ((A(17).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(9) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(9).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(9) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(1).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(9) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(17).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(9).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(9).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA10: FDCPE port map (DQ_DATA(10),DQ_DATA_D(10),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(10) <= ((A(18).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(10) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(10).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(10) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(2).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(10) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(18).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(10).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(10).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA11: FDCPE port map (DQ_DATA(11),DQ_DATA_D(11),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(11) <= ((A(19).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(11) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(11).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(11) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(3).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(11) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(19).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(11).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(11).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA12: FDCPE port map (DQ_DATA(12),DQ_DATA_D(12),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(12) <= ((A(20).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(12) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(12).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(12) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(4).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(12) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(20).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(12).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(12).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA13: FDCPE port map (DQ_DATA(13),DQ_DATA_D(13),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(13) <= ((A(21).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(13) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(13).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(13) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(5).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(13) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(21).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(13).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(13).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA14: FDCPE port map (DQ_DATA(14),DQ_DATA_D(14),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(14) <= ((A(22).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(14) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(14).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(14) <= ((D(14).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (dq_swap AND LAN_SM_FSM_FFd12 AND D(6).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(14) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(22).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(14).PIN AND $OpTx$FX_DC$6));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA15: FDCPE port map (DQ_DATA(15),DQ_DATA_D(15),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(15) <= ((A(23).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(15) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(15).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(15) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(7).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(15) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(23).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(15).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(15).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
DTACK_I <= '0';
|
||||
@@ -427,7 +523,7 @@ DTACK_I <= '0';
|
||||
<br/> DTACK_OE <= N0$BUF7/N0$BUF7_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_9_IOBUFE/D_9_IOBUFE_TRST <= (($OpTx$FX_DC$19)
|
||||
D_9_IOBUFE/D_9_IOBUFE_TRST <= (($OpTx$FX_DC$24)
|
||||
<br/> OR (RW AND NOT FCS AND autoconfig AND NOT Z3_DS/Z3_DS_D2));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Dout10: FDCPE port map (Dout1(0),Dout1_D(0),CLK_EXT,'0',NOT RESET);
|
||||
@@ -492,6 +588,14 @@ FDCPE_Dout17: FDCPE port map (Dout1(7),Dout1_D(7),CLK_EXT,'0',NOT RESET);
|
||||
<br/> NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
IDE_A(0) <= '1';
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
@@ -553,26 +657,26 @@ FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),LAN_RST_SM_FSM_FFd1,CLK_EXT,RES
|
||||
FDCPE_LAN_D_INIT8: FDCPE port map (LAN_D_INIT(8),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_INT_ENABLE: FDCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_D,CLK_EXT,NOT RESET,'0');
|
||||
<br/> LAN_INT_ENABLE_D <= ((D(15).PIN AND $OpTx$FX_DC$25)
|
||||
<br/> OR (LAN_INT_ENABLE AND NOT $OpTx$FX_DC$25));
|
||||
<br/> LAN_INT_ENABLE_D <= ((D(15).PIN AND $OpTx$FX_DC$30)
|
||||
<br/> OR (LAN_INT_ENABLE AND NOT $OpTx$FX_DC$30));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,CLK_EXT,'0',NOT RESET);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,CLK_EXT,'0',NOT RESET);
|
||||
<br/> LAN_IRQ_OUT_D <= ((NOT LAN_INT AND LAN_IRQ_D0)
|
||||
<br/> OR (NOT D(14).PIN AND LAN_INT_ENABLE AND NOT LAN_INT AND
|
||||
<br/> $OpTx$FX_DC$25)
|
||||
<br/> $OpTx$FX_DC$30)
|
||||
<br/> OR (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT AND NOT LAN_INT AND
|
||||
<br/> NOT $OpTx$FX_DC$25));
|
||||
<br/> NOT $OpTx$FX_DC$30));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
LAN_RD <= (LAN_RD_S AND $OpTx$FX_DC$22);
|
||||
LAN_RD <= (LAN_RD_S AND $OpTx$FX_DC$27);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_RD_S_D <= ((NOT RW AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd11)
|
||||
<br/> OR (NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd11 AND NOT $OpTx$FX_SC$29));
|
||||
<br/> NOT LAN_SM_FSM_FFd11 AND NOT $OpTx$FX_SC$34));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_LAN_RST_SM_FSM_FFd1: FTCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_T,CLK_EXT,RESET,'0');
|
||||
<br/> LAN_RST_SM_FSM_FFd1_T <= (NOT LAN_RST_SM_FSM_FFd1 AND LAN_RST_SM_FSM_FFd2 AND
|
||||
@@ -592,12 +696,11 @@ FDCPE_LAN_SM_FSM_FFd1: FDCPE port map (LAN_SM_FSM_FFd1,LAN_SM_FSM_FFd1_D,CLK_EXT
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd10: FDCPE port map (LAN_SM_FSM_FFd10,LAN_SM_FSM_FFd10_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_SM_FSM_FFd10_D <= ((LAN_SM_FSM_FFd6)
|
||||
<br/> OR (RW AND LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
|
||||
<br/> NOT Z3_DS/Z3_DS_D2 AND $OpTx$FX_DC$4));
|
||||
<br/> OR (RW AND $OpTx$FX_DC$5 AND $OpTx$FX_SC$34));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd11: FDCPE port map (LAN_SM_FSM_FFd11,LAN_SM_FSM_FFd11_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_SM_FSM_FFd11_D <= (RW AND LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
|
||||
<br/> NOT $OpTx$FX_DC$4);
|
||||
<br/> LAN_SM_FSM_FFd11_D <= (LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
|
||||
<br/> NOT $OpTx$FX_DC$5 AND NOT BUF_LAN_SM_FSM_FFd9);
|
||||
</td></tr><tr><td>
|
||||
FTCPE_LAN_SM_FSM_FFd12: FTCPE port map (LAN_SM_FSM_FFd12,LAN_SM_FSM_FFd12_T,CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> LAN_SM_FSM_FFd12_T <= (LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
|
||||
@@ -607,7 +710,7 @@ FDCPE_LAN_SM_FSM_FFd2: FDCPE port map (LAN_SM_FSM_FFd2,LAN_SM_FSM_FFd8,CLK_EXT,L
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd3: FDCPE port map (LAN_SM_FSM_FFd3,LAN_SM_FSM_FFd3_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_SM_FSM_FFd3_D <= ((LAN_SM_FSM_FFd4)
|
||||
<br/> OR (LAN_SM_FSM_FFd3 AND $OpTx$FX_DC$18));
|
||||
<br/> OR (LAN_SM_FSM_FFd3 AND $OpTx$FX_DC$23));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd4: FDCPE port map (LAN_SM_FSM_FFd4,LAN_SM_FSM_FFd9,CLK_EXT,LAN_SM_RST,'0');
|
||||
</td></tr><tr><td>
|
||||
@@ -615,15 +718,15 @@ FDCPE_LAN_SM_FSM_FFd5: FDCPE port map (LAN_SM_FSM_FFd5,LAN_SM_FSM_FFd5_D,CLK_EXT
|
||||
<br/> LAN_SM_FSM_FFd5_D <= (NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd10);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd6: FDCPE port map (LAN_SM_FSM_FFd6,LAN_SM_FSM_FFd6_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_SM_FSM_FFd6_D <= (LAN_SM_FSM_FFd7 AND NOT $OpTx$FX_DC$18);
|
||||
<br/> LAN_SM_FSM_FFd6_D <= (LAN_SM_FSM_FFd7 AND NOT $OpTx$FX_DC$23);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd7: FDCPE port map (LAN_SM_FSM_FFd7,LAN_SM_FSM_FFd7_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_SM_FSM_FFd7_D <= ((LAN_SM_FSM_FFd11)
|
||||
<br/> OR (LAN_SM_FSM_FFd7 AND $OpTx$FX_DC$18));
|
||||
<br/> OR (LAN_SM_FSM_FFd7 AND $OpTx$FX_DC$23));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd8: FDCPE port map (LAN_SM_FSM_FFd8,LAN_SM_FSM_FFd8_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_SM_FSM_FFd8_D <= ((LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$18)
|
||||
<br/> OR (NOT RW AND NOT BUF_LAN_SM_FSM_FFd9 AND $OpTx$FX_SC$29));
|
||||
<br/> LAN_SM_FSM_FFd8_D <= ((LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$23)
|
||||
<br/> OR (NOT RW AND NOT BUF_LAN_SM_FSM_FFd9 AND $OpTx$FX_SC$34));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd9: FDCPE port map (LAN_SM_FSM_FFd9,BUF_LAN_SM_FSM_FFd9,CLK_EXT,LAN_SM_RST,'0');
|
||||
</td></tr><tr><td>
|
||||
@@ -631,16 +734,16 @@ FDCPE_LAN_SM_RST: FDCPE port map (LAN_SM_RST,LAN_SM_RST_D,CLK_EXT,'0','0');
|
||||
<br/> LAN_SM_RST_D <= (RESET AND NOT FCS AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
LAN_WRH <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$22)
|
||||
<br/> OR (LAN_WRH_S AND $OpTx$FX_DC$22));
|
||||
LAN_WRH <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$27)
|
||||
<br/> OR (LAN_WRH_S AND $OpTx$FX_DC$27));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_WRH_S_D <= ((NOT LDS AND LAN_SM_FSM_FFd9)
|
||||
<br/> OR (NOT DS0 AND LAN_SM_FSM_FFd8));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
LAN_WRL <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$22)
|
||||
<br/> OR (LAN_WRL_S AND $OpTx$FX_DC$22));
|
||||
LAN_WRL <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$27)
|
||||
<br/> OR (LAN_WRL_S AND $OpTx$FX_DC$27));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_WRL_S_D <= ((NOT UDS AND LAN_SM_FSM_FFd9)
|
||||
@@ -716,51 +819,83 @@ FDCPE_Z3_ADR_1: FDCPE port map (Z3_ADR_1,A(3),NOT FCS,'0',NOT lan_adr/lan_adr_RS
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_A_LOW: FDCPE port map (Z3_A_LOW,Z3_A_LOW_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> Z3_A_LOW_D <= ((NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$4 AND $OpTx$FX_DC$18)
|
||||
<br/> NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$5 AND $OpTx$FX_DC$23)
|
||||
<br/> OR (NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd2 AND $OpTx$FX_DC$18 AND
|
||||
<br/> NOT $OpTx$FX_SC$29)
|
||||
<br/> NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd2 AND $OpTx$FX_DC$23 AND
|
||||
<br/> NOT $OpTx$FX_SC$34)
|
||||
<br/> OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd3 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$4)
|
||||
<br/> NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd3 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_SC$29));
|
||||
<br/> NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_SC$34));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),DQ(0).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),Z3_DATA_D(16),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(16) <= ((dq_swap AND DQ(8).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(0).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),DQ(1).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),Z3_DATA_D(17),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(17) <= ((dq_swap AND DQ(9).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(1).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),DQ(2).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),Z3_DATA_D(18),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(18) <= ((dq_swap AND DQ(10).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(2).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),DQ(3).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),Z3_DATA_D(19),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(19) <= ((dq_swap AND DQ(11).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(3).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),DQ(4).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),Z3_DATA_D(20),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(20) <= ((dq_swap AND DQ(12).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(4).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),DQ(5).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),Z3_DATA_D(21),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(21) <= ((dq_swap AND DQ(13).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(5).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),DQ(6).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),Z3_DATA_D(22),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(22) <= ((dq_swap AND DQ(14).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(6).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),DQ(7).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),Z3_DATA_D(23),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(23) <= ((dq_swap AND DQ(15).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(7).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),DQ(8).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),Z3_DATA_D(24),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(24) <= ((dq_swap AND DQ(0).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(8).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),DQ(9).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),Z3_DATA_D(25),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(25) <= ((dq_swap AND DQ(1).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(9).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),DQ(10).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),Z3_DATA_D(26),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(26) <= ((dq_swap AND DQ(2).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(10).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),DQ(11).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),Z3_DATA_D(27),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(27) <= ((dq_swap AND DQ(3).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(11).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),DQ(12).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),Z3_DATA_D(28),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(28) <= ((dq_swap AND DQ(4).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(12).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),DQ(13).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),Z3_DATA_D(29),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(29) <= ((dq_swap AND DQ(5).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(13).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),DQ(14).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),Z3_DATA_D(30),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(30) <= ((dq_swap AND DQ(6).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(14).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),DQ(15).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),Z3_DATA_D(31),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(31) <= ((dq_swap AND DQ(7).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(15).PIN));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
Z3_DS/Z3_DS_D2 <= ($OpTx$FX_DC$4 AND $OpTx$FX_DC$18);
|
||||
Z3_DS/Z3_DS_D2 <= ($OpTx$FX_DC$5 AND $OpTx$FX_DC$23);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,NOT FCS,NOT lan_adr/lan_adr_RSTF,'0');
|
||||
<br/> autoconfig_D <= (Z3 AND D(9).PIN AND D(8).PIN AND D(14).PIN AND
|
||||
@@ -768,6 +903,16 @@ FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,NOT FCS,NOT lan_adr/la
|
||||
<br/> NOT CFIN AND NOT A(20).PIN AND NOT A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND
|
||||
<br/> NOT A(16).PIN AND NOT A(23).PIN AND NOT A(22).PIN AND NOT A(21).PIN AND CFOUT);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_dq_swap: FDCPE port map (dq_swap,dq_swap_D,NOT FCS,NOT lan_adr/lan_adr_RSTF,'0');
|
||||
<br/> dq_swap_D <= ((Z3 AND NOT D(9).PIN AND NOT D(8).PIN AND D(14).PIN AND
|
||||
<br/> NOT D(13).PIN AND NOT D(12).PIN AND NOT D(11).PIN AND NOT D(10).PIN AND NOT D(15).PIN AND
|
||||
<br/> NOT A(20).PIN AND NOT A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND NOT A(16).PIN AND
|
||||
<br/> NOT A(23).PIN AND NOT A(22).PIN AND NOT A(21).PIN AND NOT SHUT_UP AND NOT A(13).PIN)
|
||||
<br/> OR (Z3 AND NOT D(9).PIN AND NOT D(8).PIN AND D(14).PIN AND
|
||||
<br/> NOT D(13).PIN AND NOT D(12).PIN AND NOT D(11).PIN AND NOT D(10).PIN AND NOT D(15).PIN AND
|
||||
<br/> NOT A(20).PIN AND NOT A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND NOT A(16).PIN AND
|
||||
<br/> NOT A(23).PIN AND NOT A(22).PIN AND NOT A(21).PIN AND NOT SHUT_UP AND NOT A(14).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_lan_adr: FDCPE port map (lan_adr,lan_adr_D,NOT FCS,NOT lan_adr/lan_adr_RSTF,'0');
|
||||
<br/> lan_adr_D <= (Z3 AND NOT D(9).PIN AND NOT D(8).PIN AND D(14).PIN AND
|
||||
<br/> NOT D(13).PIN AND NOT D(12).PIN AND NOT D(11).PIN AND NOT D(10).PIN AND NOT D(15).PIN AND
|
||||
@@ -779,7 +924,7 @@ lan_adr/lan_adr_RSTF <= (RESET AND BERR);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_lan_rdy: FDCPE port map (lan_rdy,lan_rdy_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> lan_rdy_D <= ((NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd1 AND
|
||||
<br/> NOT $OpTx$FX_DC$18)
|
||||
<br/> NOT $OpTx$FX_DC$23)
|
||||
<br/> OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1));
|
||||
</td></tr><tr><td>
|
||||
|
||||
+1388
-1240
File diff suppressed because it is too large
Load Diff
@@ -30,7 +30,7 @@
|
||||
<tr>
|
||||
<td width="40%"> <b>Date</b>
|
||||
</td>
|
||||
<td width="60%"> 12-17-2018, 11:55PM</td>
|
||||
<td width="60%"> 12-18-2018, 0:00AM</td>
|
||||
</tr>
|
||||
</table></span><br><span id="sumres" class="pgRef"><h5 align="center">RESOURCES SUMMARY</h5>
|
||||
<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
|
||||
@@ -42,11 +42,11 @@
|
||||
<th width="20%">Function Block Inputs Used</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="20%" align="center">192/288 (67%)</td>
|
||||
<td width="20%" align="center">453/1440 (32%)</td>
|
||||
<td width="20%" align="center">105/288 (37%)</td>
|
||||
<td width="20%" align="center">193/288 (68%)</td>
|
||||
<td width="20%" align="center">521/1440 (37%)</td>
|
||||
<td width="20%" align="center">106/288 (37%)</td>
|
||||
<td width="20%" align="center">109/117 (94%)</td>
|
||||
<td width="20%" align="center">359/864 (42%)</td>
|
||||
<td width="20%" align="center">366/864 (43%)</td>
|
||||
</tr>
|
||||
</table></span><br><span id="pinres" class="pgRef"><h5 align="center">PIN RESOURCES</h5>
|
||||
<table align="center" width="90%" border="0" cellspacing="0" cellpadding="0"><tr>
|
||||
@@ -123,7 +123,7 @@
|
||||
<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
|
||||
<tr>
|
||||
<td width="50%"> Macrocells in high performance mode (MCHP)</td>
|
||||
<td width="50%"> 192</td>
|
||||
<td width="50%"> 193</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="50%"> Macrocells in low power mode (MCLP)</td>
|
||||
@@ -131,7 +131,7 @@
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="50%"> Total macrocells used (MC)</td>
|
||||
<td width="50%"> 192</td>
|
||||
<td width="50%"> 193</td>
|
||||
</tr>
|
||||
</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
|
||||
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Mon Dec 17 23:54:58 2018">
|
||||
<application stringID="NgdBuild" timeStamp="Mon Dec 17 23:59:30 2018">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@@ -70,33 +70,33 @@
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="193"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="18"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="258"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="34"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="25"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="26"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="42"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="34"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="19"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="189"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="239"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="146"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="195"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="22"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="1"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="193"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="18"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="258"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="34"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="69"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="70"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="74"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="189"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="239"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="146"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="195"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="22"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
12-17-2018 11:55PM
|
||||
12-18-2018 0:00AM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The comma ','
|
||||
|
||||
|
@@ -2,7 +2,7 @@
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>LAN_IDE_CP Project Status (12/17/2018 - 23:54:59)</B></TD></TR>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>LAN_IDE_CP Project Status (12/17/2018 - 23:59:32)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>LAN_IDE.xise</TD>
|
||||
@@ -25,7 +25,7 @@ No Errors</TD>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/*.xmsgs?&DataKey=Warning'>55 Warnings (0 new)</A></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/*.xmsgs?&DataKey=Warning'>53 Warnings (0 new)</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
@@ -65,9 +65,9 @@ System Settings</A>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mo 17. Dez 23:54:50 2018</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/xst.xmsgs?&DataKey=Warning'>54 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/xst.xmsgs?&DataKey=Info'>10 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mo 17. Dez 23:54:58 2018</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Out of Date</TD><TD>Mo 17. Dez 23:51:08 2018</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>8 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mo 17. Dez 23:59:23 2018</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/xst.xmsgs?&DataKey=Warning'>52 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/xst.xmsgs?&DataKey=Info'>10 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mo 17. Dez 23:59:31 2018</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Out of Date</TD><TD>Mo 17. Dez 23:59:03 2018</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>8 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
@@ -77,5 +77,5 @@ System Settings</A>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 12/17/2018 - 23:54:59</center>
|
||||
<br><center><b>Date Generated:</b> 12/17/2018 - 23:59:32</center>
|
||||
</BODY></HTML>
|
||||
@@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Mon Dec 17 23:54:42 2018">
|
||||
<application stringID="Xst" timeStamp="Mon Dec 17 23:59:15 2018">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@@ -80,12 +80,13 @@
|
||||
</section>
|
||||
<section stringID="XST_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_ROMS" value="1"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="53">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="48"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="54">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="49"/>
|
||||
<item dataType="int" stringID="XST_14BIT_REGISTER" value="2"/>
|
||||
<item dataType="int" stringID="XST_16BIT_REGISTER" value="2"/>
|
||||
<item dataType="int" stringID="XST_8BIT_REGISTER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="1"></item>
|
||||
<item dataType="int" stringID="XST_TRISTATES" value="27">
|
||||
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="25"/>
|
||||
</item>
|
||||
@@ -93,8 +94,8 @@
|
||||
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_FSMS" value="2"/>
|
||||
<item dataType="int" stringID="XST_ROMS" value="1"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="47">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="47"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="48">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="48"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_REPORT">
|
||||
@@ -114,19 +115,19 @@
|
||||
<item stringID="XST_IOS" value="116"/>
|
||||
</section>
|
||||
<section stringID="XST_CELL_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="599">
|
||||
<item dataType="int" stringID="XST_AND2" value="193"/>
|
||||
<item dataType="int" stringID="XST_AND3" value="18"/>
|
||||
<item dataType="int" stringID="XST_BELS" value="779">
|
||||
<item dataType="int" stringID="XST_AND2" value="258"/>
|
||||
<item dataType="int" stringID="XST_AND3" value="34"/>
|
||||
<item dataType="int" stringID="XST_AND4" value="7"/>
|
||||
<item dataType="int" stringID="XST_GND" value="1"/>
|
||||
<item dataType="int" stringID="XST_INV" value="189"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="146"/>
|
||||
<item dataType="int" stringID="XST_INV" value="239"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="195"/>
|
||||
<item dataType="int" stringID="XST_VCC" value="1"/>
|
||||
<item dataType="int" stringID="XST_XOR2" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="105">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="106">
|
||||
<item dataType="int" stringID="XST_FD" value="1"/>
|
||||
<item dataType="int" stringID="XST_FDC" value="25"/>
|
||||
<item dataType="int" stringID="XST_FDC" value="26"/>
|
||||
<item dataType="int" stringID="XST_FDCE" value="3"/>
|
||||
<item dataType="int" stringID="XST_FDP" value="42"/>
|
||||
<item dataType="int" stringID="XST_FDPE" value="34"/>
|
||||
@@ -139,7 +140,7 @@
|
||||
</section>
|
||||
<section stringID="XST_ERRORS_STATISTICS">
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="54"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="52"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="10"/>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
@@ -1,2 +1,2 @@
|
||||
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1545087290
|
||||
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1545087563
|
||||
OK
|
||||
|
||||
@@ -5,10 +5,6 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="Xst" num="819" delta="old" >"<arg fmt="%s" index="1">C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd</arg>" line <arg fmt="%d" index="2">291</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
|
||||
<arg fmt="%s" index="3"><LAN_SM_RST></arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2561" delta="old" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
</msg>
|
||||
|
||||
@@ -51,9 +47,6 @@
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">C1</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="646" delta="old" >Signal <<arg fmt="%s" index="1">dq_swap</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="646" delta="old" >Signal <<arg fmt="%s" index="1">LAN_BASEADR</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2018-12-17T21:46:07</DateModified>
|
||||
<DateModified>2018-12-18T00:00:00</DateModified>
|
||||
<ModuleName>LAN_IDE_CP</ModuleName>
|
||||
<SummaryTimeStamp>2018-12-17T21:44:27</SummaryTimeStamp>
|
||||
<SummaryTimeStamp>2018-12-17T23:59:32</SummaryTimeStamp>
|
||||
<SavedFilePath>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\</ImplementationReportsDirectory>
|
||||
<DateInitialized>2016-12-13T22:08:29</DateInitialized>
|
||||
|
||||
+977
-245
File diff suppressed because it is too large
Load Diff
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pn" timeStamp="Mon Dec 17 23:54:41 2018">
|
||||
<application name="pn" timeStamp="Mon Dec 17 23:59:14 2018">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="0" type="project"/>
|
||||
<property name="ProjectIteration" value="0" type="project"/>
|
||||
|
||||
Binary file not shown.
@@ -1,2 +1,2 @@
|
||||
AR lan_ide_cp behavioral C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd sub00/vhpl01 1545087283
|
||||
EN lan_ide_cp NULL C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd sub00/vhpl00 1545087282
|
||||
AR lan_ide_cp behavioral C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd sub00/vhpl01 1545087556
|
||||
EN lan_ide_cp NULL C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd sub00/vhpl00 1545087555
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
V3 3
|
||||
FL C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd 2018/12/17.23:54:40 P.20131013
|
||||
EN work/LAN_IDE_CP 1545087282 \
|
||||
FL C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd 2018/12/17.23:58:53 P.20131013
|
||||
EN work/LAN_IDE_CP 1545087555 \
|
||||
FL C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd \
|
||||
PB ieee/std_logic_1164 1381692176 PB ieee/std_logic_arith 1381692177 \
|
||||
PB ieee/STD_LOGIC_UNSIGNED 1381692179
|
||||
AR work/LAN_IDE_CP/Behavioral 1545087283 \
|
||||
AR work/LAN_IDE_CP/Behavioral 1545087556 \
|
||||
FL C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd \
|
||||
EN work/LAN_IDE_CP 1545087282
|
||||
EN work/LAN_IDE_CP 1545087555
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Reference in New Issue
Block a user