Byteswap working
This commit is contained in:
MHeinrichs
File diff suppressed because it is too large
Load Diff
@@ -6,95 +6,127 @@
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********** Mapped Logic **********
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</td></tr><tr><td>
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</td></tr><tr><td>
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$OpTx$FX_DC$14 <= (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5 AND
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$OpTx$FX_DC$16 <= (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5 AND
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<br/> NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
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<br/> NOT LAN_SM_FSM_FFd9 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd11 AND
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<br/> NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd4);
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</td></tr><tr><td>
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</td></tr><tr><td>
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$OpTx$FX_DC$18 <= (DS1 AND DS0);
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$OpTx$FX_DC$23 <= (DS1 AND DS0);
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</td></tr><tr><td>
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</td></tr><tr><td>
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$OpTx$FX_DC$19 <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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$OpTx$FX_DC$24 <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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</td></tr><tr><td>
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$OpTx$FX_DC$22 <= (RESET AND NOT FCS);
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$OpTx$FX_DC$27 <= (RESET AND NOT FCS);
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</td></tr><tr><td>
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</td></tr><tr><td>
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$OpTx$FX_DC$25 <= (NOT RW AND lan_adr AND Z3_ADR(13) AND NOT Z3_DS/Z3_DS_D2);
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$OpTx$FX_DC$30 <= (NOT RW AND lan_adr AND Z3_ADR(13) AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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</td></tr><tr><td>
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$OpTx$FX_DC$4 <= (UDS AND LDS);
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$OpTx$FX_DC$5 <= (UDS AND LDS);
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</td></tr><tr><td>
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</td></tr><tr><td>
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$OpTx$FX_DC$7 <= ((LAN_SM_FSM_FFd3)
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<br/> OR (LAN_SM_FSM_FFd12 AND $OpTx$FX_DC$4));
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$OpTx$FX_DC$6 <= ((LAN_SM_FSM_FFd3)
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<br/> OR (LAN_SM_FSM_FFd12 AND $OpTx$FX_DC$5));
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</td></tr><tr><td>
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</td></tr><tr><td>
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$OpTx$FX_SC$29 <= (LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
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$OpTx$FX_SC$34 <= (LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
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<br/> NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A8: FDCPE port map (A_I(8),DQ(0).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A8: FDCPE port map (A_I(8),A(8),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(8) <= ((dq_swap AND DQ(8).PIN)
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<br/> OR (NOT dq_swap AND DQ(0).PIN));
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<br/> A(8) <= A_I(8) when A_OE(8) = '1' else 'Z';
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<br/> A_OE(8) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A9: FDCPE port map (A_I(9),DQ(1).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A9: FDCPE port map (A_I(9),A(9),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(9) <= ((dq_swap AND DQ(9).PIN)
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<br/> OR (NOT dq_swap AND DQ(1).PIN));
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<br/> A(9) <= A_I(9) when A_OE(9) = '1' else 'Z';
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<br/> A_OE(9) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A10: FDCPE port map (A_I(10),DQ(2).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A10: FDCPE port map (A_I(10),A(10),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(10) <= ((dq_swap AND DQ(10).PIN)
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<br/> OR (NOT dq_swap AND DQ(2).PIN));
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<br/> A(10) <= A_I(10) when A_OE(10) = '1' else 'Z';
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<br/> A_OE(10) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A11: FDCPE port map (A_I(11),DQ(3).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A11: FDCPE port map (A_I(11),A(11),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(11) <= ((dq_swap AND DQ(11).PIN)
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<br/> OR (NOT dq_swap AND DQ(3).PIN));
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<br/> A(11) <= A_I(11) when A_OE(11) = '1' else 'Z';
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<br/> A_OE(11) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A12: FDCPE port map (A_I(12),DQ(4).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A12: FDCPE port map (A_I(12),A(12),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(12) <= ((dq_swap AND DQ(12).PIN)
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<br/> OR (NOT dq_swap AND DQ(4).PIN));
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<br/> A(12) <= A_I(12) when A_OE(12) = '1' else 'Z';
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<br/> A_OE(12) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A13: FDCPE port map (A_I(13),DQ(5).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A13: FDCPE port map (A_I(13),A(13),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(13) <= ((dq_swap AND DQ(13).PIN)
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<br/> OR (NOT dq_swap AND DQ(5).PIN));
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<br/> A(13) <= A_I(13) when A_OE(13) = '1' else 'Z';
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<br/> A_OE(13) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A14: FDCPE port map (A_I(14),DQ(6).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A14: FDCPE port map (A_I(14),A(14),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(14) <= ((dq_swap AND DQ(14).PIN)
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<br/> OR (NOT dq_swap AND DQ(6).PIN));
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<br/> A(14) <= A_I(14) when A_OE(14) = '1' else 'Z';
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<br/> A_OE(14) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A15: FDCPE port map (A_I(15),DQ(7).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A15: FDCPE port map (A_I(15),A(15),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(15) <= ((dq_swap AND DQ(15).PIN)
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<br/> OR (NOT dq_swap AND DQ(7).PIN));
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<br/> A(15) <= A_I(15) when A_OE(15) = '1' else 'Z';
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<br/> A_OE(15) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A16: FDCPE port map (A_I(16),DQ(8).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A16: FDCPE port map (A_I(16),A(16),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(16) <= ((dq_swap AND DQ(0).PIN)
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<br/> OR (NOT dq_swap AND DQ(8).PIN));
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<br/> A(16) <= A_I(16) when A_OE(16) = '1' else 'Z';
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<br/> A_OE(16) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A17: FDCPE port map (A_I(17),DQ(9).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A17: FDCPE port map (A_I(17),A(17),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(17) <= ((dq_swap AND DQ(1).PIN)
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<br/> OR (NOT dq_swap AND DQ(9).PIN));
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<br/> A(17) <= A_I(17) when A_OE(17) = '1' else 'Z';
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<br/> A_OE(17) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A18: FDCPE port map (A_I(18),DQ(10).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A18: FDCPE port map (A_I(18),A(18),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(18) <= ((dq_swap AND DQ(2).PIN)
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<br/> OR (NOT dq_swap AND DQ(10).PIN));
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<br/> A(18) <= A_I(18) when A_OE(18) = '1' else 'Z';
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<br/> A_OE(18) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A19: FDCPE port map (A_I(19),DQ(11).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A19: FDCPE port map (A_I(19),A(19),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(19) <= ((dq_swap AND DQ(3).PIN)
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<br/> OR (NOT dq_swap AND DQ(11).PIN));
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<br/> A(19) <= A_I(19) when A_OE(19) = '1' else 'Z';
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<br/> A_OE(19) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A20: FDCPE port map (A_I(20),DQ(12).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A20: FDCPE port map (A_I(20),A(20),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(20) <= ((dq_swap AND DQ(4).PIN)
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<br/> OR (NOT dq_swap AND DQ(12).PIN));
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<br/> A(20) <= A_I(20) when A_OE(20) = '1' else 'Z';
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<br/> A_OE(20) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A21: FDCPE port map (A_I(21),DQ(13).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A21: FDCPE port map (A_I(21),A(21),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(21) <= ((dq_swap AND DQ(5).PIN)
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<br/> OR (NOT dq_swap AND DQ(13).PIN));
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<br/> A(21) <= A_I(21) when A_OE(21) = '1' else 'Z';
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<br/> A_OE(21) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A22: FDCPE port map (A_I(22),DQ(14).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A22: FDCPE port map (A_I(22),A(22),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(22) <= ((dq_swap AND DQ(6).PIN)
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<br/> OR (NOT dq_swap AND DQ(14).PIN));
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<br/> A(22) <= A_I(22) when A_OE(22) = '1' else 'Z';
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<br/> A_OE(22) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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FDCPE_A23: FDCPE port map (A_I(23),DQ(15).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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FDCPE_A23: FDCPE port map (A_I(23),A(23),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
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<br/> A(23) <= ((dq_swap AND DQ(7).PIN)
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<br/> OR (NOT dq_swap AND DQ(15).PIN));
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<br/> A(23) <= A_I(23) when A_OE(23) = '1' else 'Z';
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<br/> A_OE(23) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
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</td></tr><tr><td>
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@@ -149,7 +181,7 @@ A_LAN(13) <= NOT ((RESET AND NOT Z3_ADR(12)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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BUF_LAN_SM_FSM_FFd9 <= (NOT RW AND LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
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<br/> NOT $OpTx$FX_DC$4);
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<br/> NOT $OpTx$FX_DC$5);
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</td></tr><tr><td>
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FDCPE_CFOUT: FDCPE port map (CFOUT,CFOUT_D,CLK_EXT,'0',NOT RESET,FCS);
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<br/> CFOUT_D <= (NOT AUTO_CONFIG_DONE_CYCLE AND AUTOBOOT_OFF);
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@@ -164,90 +196,90 @@ CP_RD <= '1';
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CP_WE <= '1';
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</td></tr><tr><td>
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</td></tr><tr><td>
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D_I(0) <= NOT ((NOT Z3_DATA(16) AND $OpTx$FX_DC$19));
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D_I(0) <= NOT ((NOT Z3_DATA(16) AND $OpTx$FX_DC$24));
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<br/> D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
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<br/> D_OE(0) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
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</td></tr><tr><td>
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</td></tr><tr><td>
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D_I(1) <= NOT ((NOT Z3_DATA(17) AND $OpTx$FX_DC$19));
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D_I(1) <= NOT ((NOT Z3_DATA(17) AND $OpTx$FX_DC$24));
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<br/> D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
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<br/> D_OE(1) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
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</td></tr><tr><td>
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</td></tr><tr><td>
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D_I(2) <= NOT ((NOT Z3_DATA(18) AND $OpTx$FX_DC$19));
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D_I(2) <= NOT ((NOT Z3_DATA(18) AND $OpTx$FX_DC$24));
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<br/> D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
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<br/> D_OE(2) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
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</td></tr><tr><td>
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</td></tr><tr><td>
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D_I(3) <= NOT ((NOT Z3_DATA(19) AND $OpTx$FX_DC$19));
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D_I(3) <= NOT ((NOT Z3_DATA(19) AND $OpTx$FX_DC$24));
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<br/> D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
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<br/> D_OE(3) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
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</td></tr><tr><td>
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</td></tr><tr><td>
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D_I(4) <= NOT ((NOT Z3_DATA(20) AND $OpTx$FX_DC$19));
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D_I(4) <= NOT ((NOT Z3_DATA(20) AND $OpTx$FX_DC$24));
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<br/> D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
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<br/> D_OE(4) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
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</td></tr><tr><td>
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</td></tr><tr><td>
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D_I(5) <= NOT ((NOT Z3_DATA(21) AND $OpTx$FX_DC$19));
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D_I(5) <= NOT ((NOT Z3_DATA(21) AND $OpTx$FX_DC$24));
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<br/> D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
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<br/> D_OE(5) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
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</td></tr><tr><td>
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</td></tr><tr><td>
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D_I(6) <= NOT ((NOT Z3_DATA(22) AND $OpTx$FX_DC$19));
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D_I(6) <= NOT ((NOT Z3_DATA(22) AND $OpTx$FX_DC$24));
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<br/> D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
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<br/> D_OE(6) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
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</td></tr><tr><td>
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</td></tr><tr><td>
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D_I(7) <= NOT ((NOT Z3_DATA(23) AND $OpTx$FX_DC$19));
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D_I(7) <= NOT ((NOT Z3_DATA(23) AND $OpTx$FX_DC$24));
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<br/> D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
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<br/> D_OE(7) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
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</td></tr><tr><td>
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</td></tr><tr><td>
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D_I(8) <= ((Z3_DATA(24) AND $OpTx$FX_DC$19)
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<br/> OR (Dout1(0) AND NOT $OpTx$FX_DC$19));
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D_I(8) <= ((Z3_DATA(24) AND $OpTx$FX_DC$24)
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<br/> OR (Dout1(0) AND NOT $OpTx$FX_DC$24));
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<br/> D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
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<br/> D_OE(8) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
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</td></tr><tr><td>
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</td></tr><tr><td>
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D_I(9) <= ((Z3_DATA(25) AND $OpTx$FX_DC$19)
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<br/> OR (Dout1(1) AND NOT $OpTx$FX_DC$19));
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D_I(9) <= ((Z3_DATA(25) AND $OpTx$FX_DC$24)
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<br/> OR (Dout1(1) AND NOT $OpTx$FX_DC$24));
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<br/> D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
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<br/> D_OE(9) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
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</td></tr><tr><td>
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</td></tr><tr><td>
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D_I(10) <= ((Z3_DATA(26) AND $OpTx$FX_DC$19)
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<br/> OR (Dout1(2) AND NOT $OpTx$FX_DC$19));
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D_I(10) <= ((Z3_DATA(26) AND $OpTx$FX_DC$24)
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<br/> OR (Dout1(2) AND NOT $OpTx$FX_DC$24));
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<br/> D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
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<br/> D_OE(10) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
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</td></tr><tr><td>
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</td></tr><tr><td>
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D_I(11) <= ((Z3_DATA(27) AND $OpTx$FX_DC$19)
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<br/> OR (Dout1(3) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(11) <= ((Z3_DATA(27) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(3) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
|
||||
<br/> D_OE(11) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(12) <= ((Z3_DATA(28) AND $OpTx$FX_DC$19)
|
||||
<br/> OR (Dout1(4) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(12) <= ((Z3_DATA(28) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(4) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
|
||||
<br/> D_OE(12) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(13) <= ((Z3_DATA(29) AND $OpTx$FX_DC$19)
|
||||
<br/> OR (Dout1(5) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(13) <= ((Z3_DATA(29) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(5) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
|
||||
<br/> D_OE(13) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(14) <= ((Z3_DATA(30) AND $OpTx$FX_DC$19)
|
||||
<br/> OR (Dout1(6) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(14) <= ((Z3_DATA(30) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(6) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
|
||||
<br/> D_OE(14) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_I(15) <= ((Z3_DATA(31) AND $OpTx$FX_DC$19)
|
||||
<br/> OR (Dout1(7) AND NOT $OpTx$FX_DC$19));
|
||||
D_I(15) <= ((Z3_DATA(31) AND $OpTx$FX_DC$24)
|
||||
<br/> OR (Dout1(7) AND NOT $OpTx$FX_DC$24));
|
||||
<br/> D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
|
||||
<br/> D_OE(15) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
||||
</td></tr><tr><td>
|
||||
@@ -339,87 +371,151 @@ DQ_I(15) <= (RESET AND DQ_DATA(15));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST <= ((NOT RESET)
|
||||
<br/> OR (NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2 AND NOT $OpTx$FX_DC$19));
|
||||
<br/> OR (NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2 AND NOT $OpTx$FX_DC$24));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA0: FDCPE port map (DQ_DATA(0),DQ_DATA_D(0),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(0) <= ((A(8).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(0) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(0).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(0) <= ((D(8).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(0) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(16).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(8).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(0).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA1: FDCPE port map (DQ_DATA(1),DQ_DATA_D(1),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(1) <= ((DQ_DATA(1) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (A(9).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(1).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(1) <= ((D(9).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(1) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(17).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(9).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(1).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA2: FDCPE port map (DQ_DATA(2),DQ_DATA_D(2),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(2) <= ((DQ_DATA(2) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (A(10).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(2).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(2) <= ((D(10).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(2) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(18).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(10).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(2).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA3: FDCPE port map (DQ_DATA(3),DQ_DATA_D(3),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(3) <= ((DQ_DATA(3) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (A(11).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(3).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(3) <= ((D(11).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(3) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(19).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(11).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(3).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA4: FDCPE port map (DQ_DATA(4),DQ_DATA_D(4),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(4) <= ((DQ_DATA(4) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (A(12).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(4).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(4) <= ((D(12).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(4).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(4) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(20).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(12).PIN AND $OpTx$FX_DC$6));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA5: FDCPE port map (DQ_DATA(5),DQ_DATA_D(5),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(5) <= ((DQ_DATA(5) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (A(13).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(5).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(5) <= ((D(13).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(5) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(21).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(13).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(5).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA6: FDCPE port map (DQ_DATA(6),DQ_DATA_D(6),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(6) <= ((DQ_DATA(6) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (A(14).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(6).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(6) <= ((D(14).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(6) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(22).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(14).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(6).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA7: FDCPE port map (DQ_DATA(7),DQ_DATA_D(7),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(7) <= ((A(15).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(7) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (LAN_SM_FSM_FFd12 AND D(7).PIN AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(7) <= ((D(15).PIN AND dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (NOT dq_swap AND LAN_SM_FSM_FFd12 AND D(7).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(7) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(23).PIN AND dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (NOT dq_swap AND A(15).PIN AND $OpTx$FX_DC$6));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA8: FDCPE port map (DQ_DATA(8),DQ_DATA_D(8),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(8) <= ((A(16).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(8) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(8).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(8) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(0).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(8) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(16).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(8).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(8).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA9: FDCPE port map (DQ_DATA(9),DQ_DATA_D(9),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(9) <= ((A(17).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(9) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(9).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(9) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(1).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(9) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(17).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(9).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(9).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA10: FDCPE port map (DQ_DATA(10),DQ_DATA_D(10),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(10) <= ((A(18).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(10) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(10).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(10) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(2).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(10) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(18).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(10).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(10).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA11: FDCPE port map (DQ_DATA(11),DQ_DATA_D(11),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(11) <= ((A(19).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(11) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(11).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(11) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(3).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(11) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(19).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(11).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(11).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA12: FDCPE port map (DQ_DATA(12),DQ_DATA_D(12),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(12) <= ((A(20).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(12) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(12).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(12) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(4).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(12) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(20).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(12).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(12).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA13: FDCPE port map (DQ_DATA(13),DQ_DATA_D(13),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(13) <= ((A(21).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(13) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(13).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(13) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(5).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(13) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(21).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(13).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(13).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA14: FDCPE port map (DQ_DATA(14),DQ_DATA_D(14),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(14) <= ((A(22).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(14) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(14).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(14) <= ((D(14).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (dq_swap AND LAN_SM_FSM_FFd12 AND D(6).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(14) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(22).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(14).PIN AND $OpTx$FX_DC$6));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_DQ_DATA15: FDCPE port map (DQ_DATA(15),DQ_DATA_D(15),CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> DQ_DATA_D(15) <= ((A(23).PIN AND $OpTx$FX_DC$7)
|
||||
<br/> OR (DQ_DATA(15) AND NOT $OpTx$FX_DC$14)
|
||||
<br/> OR (D(15).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
|
||||
<br/> DQ_DATA_D(15) <= ((dq_swap AND LAN_SM_FSM_FFd12 AND D(7).PIN AND
|
||||
<br/> NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (DQ_DATA(15) AND NOT $OpTx$FX_DC$16)
|
||||
<br/> OR (A(23).PIN AND NOT dq_swap AND $OpTx$FX_DC$6)
|
||||
<br/> OR (dq_swap AND A(15).PIN AND $OpTx$FX_DC$6)
|
||||
<br/> OR (D(15).PIN AND NOT dq_swap AND LAN_SM_FSM_FFd12 AND
|
||||
<br/> NOT $OpTx$FX_DC$5));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
DTACK_I <= '0';
|
||||
@@ -427,7 +523,7 @@ DTACK_I <= '0';
|
||||
<br/> DTACK_OE <= N0$BUF7/N0$BUF7_TRST;
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
D_9_IOBUFE/D_9_IOBUFE_TRST <= (($OpTx$FX_DC$19)
|
||||
D_9_IOBUFE/D_9_IOBUFE_TRST <= (($OpTx$FX_DC$24)
|
||||
<br/> OR (RW AND NOT FCS AND autoconfig AND NOT Z3_DS/Z3_DS_D2));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Dout10: FDCPE port map (Dout1(0),Dout1_D(0),CLK_EXT,'0',NOT RESET);
|
||||
@@ -492,6 +588,14 @@ FDCPE_Dout17: FDCPE port map (Dout1(7),Dout1_D(7),CLK_EXT,'0',NOT RESET);
|
||||
<br/> NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
IDE_A(0) <= '1';
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
@@ -553,26 +657,26 @@ FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),LAN_RST_SM_FSM_FFd1,CLK_EXT,RES
|
||||
FDCPE_LAN_D_INIT8: FDCPE port map (LAN_D_INIT(8),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_INT_ENABLE: FDCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_D,CLK_EXT,NOT RESET,'0');
|
||||
<br/> LAN_INT_ENABLE_D <= ((D(15).PIN AND $OpTx$FX_DC$25)
|
||||
<br/> OR (LAN_INT_ENABLE AND NOT $OpTx$FX_DC$25));
|
||||
<br/> LAN_INT_ENABLE_D <= ((D(15).PIN AND $OpTx$FX_DC$30)
|
||||
<br/> OR (LAN_INT_ENABLE AND NOT $OpTx$FX_DC$30));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,CLK_EXT,'0',NOT RESET);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,CLK_EXT,'0',NOT RESET);
|
||||
<br/> LAN_IRQ_OUT_D <= ((NOT LAN_INT AND LAN_IRQ_D0)
|
||||
<br/> OR (NOT D(14).PIN AND LAN_INT_ENABLE AND NOT LAN_INT AND
|
||||
<br/> $OpTx$FX_DC$25)
|
||||
<br/> $OpTx$FX_DC$30)
|
||||
<br/> OR (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT AND NOT LAN_INT AND
|
||||
<br/> NOT $OpTx$FX_DC$25));
|
||||
<br/> NOT $OpTx$FX_DC$30));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
LAN_RD <= (LAN_RD_S AND $OpTx$FX_DC$22);
|
||||
LAN_RD <= (LAN_RD_S AND $OpTx$FX_DC$27);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_RD_S_D <= ((NOT RW AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd11)
|
||||
<br/> OR (NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd11 AND NOT $OpTx$FX_SC$29));
|
||||
<br/> NOT LAN_SM_FSM_FFd11 AND NOT $OpTx$FX_SC$34));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_LAN_RST_SM_FSM_FFd1: FTCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_T,CLK_EXT,RESET,'0');
|
||||
<br/> LAN_RST_SM_FSM_FFd1_T <= (NOT LAN_RST_SM_FSM_FFd1 AND LAN_RST_SM_FSM_FFd2 AND
|
||||
@@ -592,12 +696,11 @@ FDCPE_LAN_SM_FSM_FFd1: FDCPE port map (LAN_SM_FSM_FFd1,LAN_SM_FSM_FFd1_D,CLK_EXT
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd10: FDCPE port map (LAN_SM_FSM_FFd10,LAN_SM_FSM_FFd10_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_SM_FSM_FFd10_D <= ((LAN_SM_FSM_FFd6)
|
||||
<br/> OR (RW AND LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
|
||||
<br/> NOT Z3_DS/Z3_DS_D2 AND $OpTx$FX_DC$4));
|
||||
<br/> OR (RW AND $OpTx$FX_DC$5 AND $OpTx$FX_SC$34));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd11: FDCPE port map (LAN_SM_FSM_FFd11,LAN_SM_FSM_FFd11_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_SM_FSM_FFd11_D <= (RW AND LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
|
||||
<br/> NOT $OpTx$FX_DC$4);
|
||||
<br/> LAN_SM_FSM_FFd11_D <= (LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
|
||||
<br/> NOT $OpTx$FX_DC$5 AND NOT BUF_LAN_SM_FSM_FFd9);
|
||||
</td></tr><tr><td>
|
||||
FTCPE_LAN_SM_FSM_FFd12: FTCPE port map (LAN_SM_FSM_FFd12,LAN_SM_FSM_FFd12_T,CLK_EXT,'0',LAN_SM_RST);
|
||||
<br/> LAN_SM_FSM_FFd12_T <= (LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
|
||||
@@ -607,7 +710,7 @@ FDCPE_LAN_SM_FSM_FFd2: FDCPE port map (LAN_SM_FSM_FFd2,LAN_SM_FSM_FFd8,CLK_EXT,L
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd3: FDCPE port map (LAN_SM_FSM_FFd3,LAN_SM_FSM_FFd3_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_SM_FSM_FFd3_D <= ((LAN_SM_FSM_FFd4)
|
||||
<br/> OR (LAN_SM_FSM_FFd3 AND $OpTx$FX_DC$18));
|
||||
<br/> OR (LAN_SM_FSM_FFd3 AND $OpTx$FX_DC$23));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd4: FDCPE port map (LAN_SM_FSM_FFd4,LAN_SM_FSM_FFd9,CLK_EXT,LAN_SM_RST,'0');
|
||||
</td></tr><tr><td>
|
||||
@@ -615,15 +718,15 @@ FDCPE_LAN_SM_FSM_FFd5: FDCPE port map (LAN_SM_FSM_FFd5,LAN_SM_FSM_FFd5_D,CLK_EXT
|
||||
<br/> LAN_SM_FSM_FFd5_D <= (NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd10);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd6: FDCPE port map (LAN_SM_FSM_FFd6,LAN_SM_FSM_FFd6_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_SM_FSM_FFd6_D <= (LAN_SM_FSM_FFd7 AND NOT $OpTx$FX_DC$18);
|
||||
<br/> LAN_SM_FSM_FFd6_D <= (LAN_SM_FSM_FFd7 AND NOT $OpTx$FX_DC$23);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd7: FDCPE port map (LAN_SM_FSM_FFd7,LAN_SM_FSM_FFd7_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_SM_FSM_FFd7_D <= ((LAN_SM_FSM_FFd11)
|
||||
<br/> OR (LAN_SM_FSM_FFd7 AND $OpTx$FX_DC$18));
|
||||
<br/> OR (LAN_SM_FSM_FFd7 AND $OpTx$FX_DC$23));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd8: FDCPE port map (LAN_SM_FSM_FFd8,LAN_SM_FSM_FFd8_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_SM_FSM_FFd8_D <= ((LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$18)
|
||||
<br/> OR (NOT RW AND NOT BUF_LAN_SM_FSM_FFd9 AND $OpTx$FX_SC$29));
|
||||
<br/> LAN_SM_FSM_FFd8_D <= ((LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$23)
|
||||
<br/> OR (NOT RW AND NOT BUF_LAN_SM_FSM_FFd9 AND $OpTx$FX_SC$34));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_SM_FSM_FFd9: FDCPE port map (LAN_SM_FSM_FFd9,BUF_LAN_SM_FSM_FFd9,CLK_EXT,LAN_SM_RST,'0');
|
||||
</td></tr><tr><td>
|
||||
@@ -631,16 +734,16 @@ FDCPE_LAN_SM_RST: FDCPE port map (LAN_SM_RST,LAN_SM_RST_D,CLK_EXT,'0','0');
|
||||
<br/> LAN_SM_RST_D <= (RESET AND NOT FCS AND NOT Z3_DS/Z3_DS_D2);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
LAN_WRH <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$22)
|
||||
<br/> OR (LAN_WRH_S AND $OpTx$FX_DC$22));
|
||||
LAN_WRH <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$27)
|
||||
<br/> OR (LAN_WRH_S AND $OpTx$FX_DC$27));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_WRH_S_D <= ((NOT LDS AND LAN_SM_FSM_FFd9)
|
||||
<br/> OR (NOT DS0 AND LAN_SM_FSM_FFd8));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
LAN_WRL <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$22)
|
||||
<br/> OR (LAN_WRL_S AND $OpTx$FX_DC$22));
|
||||
LAN_WRL <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$27)
|
||||
<br/> OR (LAN_WRL_S AND $OpTx$FX_DC$27));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> LAN_WRL_S_D <= ((NOT UDS AND LAN_SM_FSM_FFd9)
|
||||
@@ -716,51 +819,83 @@ FDCPE_Z3_ADR_1: FDCPE port map (Z3_ADR_1,A(3),NOT FCS,'0',NOT lan_adr/lan_adr_RS
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_A_LOW: FDCPE port map (Z3_A_LOW,Z3_A_LOW_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> Z3_A_LOW_D <= ((NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$4 AND $OpTx$FX_DC$18)
|
||||
<br/> NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$5 AND $OpTx$FX_DC$23)
|
||||
<br/> OR (NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd2 AND $OpTx$FX_DC$18 AND
|
||||
<br/> NOT $OpTx$FX_SC$29)
|
||||
<br/> NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd2 AND $OpTx$FX_DC$23 AND
|
||||
<br/> NOT $OpTx$FX_SC$34)
|
||||
<br/> OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd3 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$4)
|
||||
<br/> NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$5)
|
||||
<br/> OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd3 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_SC$29));
|
||||
<br/> NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_SC$34));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),DQ(0).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),Z3_DATA_D(16),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(16) <= ((dq_swap AND DQ(8).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(0).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),DQ(1).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),Z3_DATA_D(17),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(17) <= ((dq_swap AND DQ(9).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(1).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),DQ(2).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),Z3_DATA_D(18),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(18) <= ((dq_swap AND DQ(10).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(2).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),DQ(3).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),Z3_DATA_D(19),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(19) <= ((dq_swap AND DQ(11).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(3).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),DQ(4).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),Z3_DATA_D(20),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(20) <= ((dq_swap AND DQ(12).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(4).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),DQ(5).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),Z3_DATA_D(21),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(21) <= ((dq_swap AND DQ(13).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(5).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),DQ(6).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),Z3_DATA_D(22),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(22) <= ((dq_swap AND DQ(14).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(6).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),DQ(7).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),Z3_DATA_D(23),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(23) <= ((dq_swap AND DQ(15).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(7).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),DQ(8).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),Z3_DATA_D(24),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(24) <= ((dq_swap AND DQ(0).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(8).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),DQ(9).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),Z3_DATA_D(25),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(25) <= ((dq_swap AND DQ(1).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(9).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),DQ(10).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),Z3_DATA_D(26),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(26) <= ((dq_swap AND DQ(2).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(10).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),DQ(11).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),Z3_DATA_D(27),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(27) <= ((dq_swap AND DQ(3).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(11).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),DQ(12).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),Z3_DATA_D(28),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(28) <= ((dq_swap AND DQ(4).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(12).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),DQ(13).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),Z3_DATA_D(29),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(29) <= ((dq_swap AND DQ(5).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(13).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),DQ(14).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),Z3_DATA_D(30),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(30) <= ((dq_swap AND DQ(6).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(14).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),DQ(15).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),Z3_DATA_D(31),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
|
||||
<br/> Z3_DATA_D(31) <= ((dq_swap AND DQ(7).PIN)
|
||||
<br/> OR (NOT dq_swap AND DQ(15).PIN));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
Z3_DS/Z3_DS_D2 <= ($OpTx$FX_DC$4 AND $OpTx$FX_DC$18);
|
||||
Z3_DS/Z3_DS_D2 <= ($OpTx$FX_DC$5 AND $OpTx$FX_DC$23);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,NOT FCS,NOT lan_adr/lan_adr_RSTF,'0');
|
||||
<br/> autoconfig_D <= (Z3 AND D(9).PIN AND D(8).PIN AND D(14).PIN AND
|
||||
@@ -768,6 +903,16 @@ FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,NOT FCS,NOT lan_adr/la
|
||||
<br/> NOT CFIN AND NOT A(20).PIN AND NOT A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND
|
||||
<br/> NOT A(16).PIN AND NOT A(23).PIN AND NOT A(22).PIN AND NOT A(21).PIN AND CFOUT);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_dq_swap: FDCPE port map (dq_swap,dq_swap_D,NOT FCS,NOT lan_adr/lan_adr_RSTF,'0');
|
||||
<br/> dq_swap_D <= ((Z3 AND NOT D(9).PIN AND NOT D(8).PIN AND D(14).PIN AND
|
||||
<br/> NOT D(13).PIN AND NOT D(12).PIN AND NOT D(11).PIN AND NOT D(10).PIN AND NOT D(15).PIN AND
|
||||
<br/> NOT A(20).PIN AND NOT A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND NOT A(16).PIN AND
|
||||
<br/> NOT A(23).PIN AND NOT A(22).PIN AND NOT A(21).PIN AND NOT SHUT_UP AND NOT A(13).PIN)
|
||||
<br/> OR (Z3 AND NOT D(9).PIN AND NOT D(8).PIN AND D(14).PIN AND
|
||||
<br/> NOT D(13).PIN AND NOT D(12).PIN AND NOT D(11).PIN AND NOT D(10).PIN AND NOT D(15).PIN AND
|
||||
<br/> NOT A(20).PIN AND NOT A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND NOT A(16).PIN AND
|
||||
<br/> NOT A(23).PIN AND NOT A(22).PIN AND NOT A(21).PIN AND NOT SHUT_UP AND NOT A(14).PIN));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_lan_adr: FDCPE port map (lan_adr,lan_adr_D,NOT FCS,NOT lan_adr/lan_adr_RSTF,'0');
|
||||
<br/> lan_adr_D <= (Z3 AND NOT D(9).PIN AND NOT D(8).PIN AND D(14).PIN AND
|
||||
<br/> NOT D(13).PIN AND NOT D(12).PIN AND NOT D(11).PIN AND NOT D(10).PIN AND NOT D(15).PIN AND
|
||||
@@ -779,7 +924,7 @@ lan_adr/lan_adr_RSTF <= (RESET AND BERR);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_lan_rdy: FDCPE port map (lan_rdy,lan_rdy_D,CLK_EXT,LAN_SM_RST,'0');
|
||||
<br/> lan_rdy_D <= ((NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd1 AND
|
||||
<br/> NOT $OpTx$FX_DC$18)
|
||||
<br/> NOT $OpTx$FX_DC$23)
|
||||
<br/> OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5 AND
|
||||
<br/> NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1));
|
||||
</td></tr><tr><td>
|
||||
|
||||
+1426
-1278
File diff suppressed because it is too large
Load Diff
@@ -30,7 +30,7 @@
|
||||
<tr>
|
||||
<td width="40%"> <b>Date</b>
|
||||
</td>
|
||||
<td width="60%"> 12-17-2018, 11:55PM</td>
|
||||
<td width="60%"> 12-18-2018, 0:00AM</td>
|
||||
</tr>
|
||||
</table></span><br><span id="sumres" class="pgRef"><h5 align="center">RESOURCES SUMMARY</h5>
|
||||
<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
|
||||
@@ -42,11 +42,11 @@
|
||||
<th width="20%">Function Block Inputs Used</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="20%" align="center">192/288 (67%)</td>
|
||||
<td width="20%" align="center">453/1440 (32%)</td>
|
||||
<td width="20%" align="center">105/288 (37%)</td>
|
||||
<td width="20%" align="center">193/288 (68%)</td>
|
||||
<td width="20%" align="center">521/1440 (37%)</td>
|
||||
<td width="20%" align="center">106/288 (37%)</td>
|
||||
<td width="20%" align="center">109/117 (94%)</td>
|
||||
<td width="20%" align="center">359/864 (42%)</td>
|
||||
<td width="20%" align="center">366/864 (43%)</td>
|
||||
</tr>
|
||||
</table></span><br><span id="pinres" class="pgRef"><h5 align="center">PIN RESOURCES</h5>
|
||||
<table align="center" width="90%" border="0" cellspacing="0" cellpadding="0"><tr>
|
||||
@@ -123,7 +123,7 @@
|
||||
<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
|
||||
<tr>
|
||||
<td width="50%"> Macrocells in high performance mode (MCHP)</td>
|
||||
<td width="50%"> 192</td>
|
||||
<td width="50%"> 193</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="50%"> Macrocells in low power mode (MCLP)</td>
|
||||
@@ -131,7 +131,7 @@
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="50%"> Total macrocells used (MC)</td>
|
||||
<td width="50%"> 192</td>
|
||||
<td width="50%"> 193</td>
|
||||
</tr>
|
||||
</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
|
||||
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||||
|
||||
Reference in New Issue
Block a user