Dominick.Vansevenant/Zorro-LAN-IDE
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Byteswap working

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This commit is contained in:
MHeinrichs
2018-12-18 00:00:58 +01:00
parent 8cbd5c7cef
commit 11a6adca8a
34 changed files with 12158 additions and 9568 deletions
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Logic/LAN_IDE/LAN_IDE_CP.vhd
+21 -21
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@@ -288,7 +288,7 @@ begin
end process lan_rst_gen;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,FCS,reset)
lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
begin
if(LAN_SM_RST ='1' ) then
LAN_SM <=nop;
@@ -314,17 +314,17 @@ begin
-- this is a quite complex thing for a cpld
-- so I have to move this out of the cycle start condition and prepare it for every loop
if(UDS='0' or LDS='0')then
--if(dq_swap='0') then
if(dq_swap='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
--else
-- DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
--end if;
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
end if;
else
--if(dq_swap='0') then
if(dq_swap='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
--else
-- DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
--end if;
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
end if;
if(lan_adr = '1' and Z3_DS = '0' and Z3_ADR(15) = '0' )then --cycle start!
@@ -356,11 +356,11 @@ begin
LAN_SM<=end_read_upper;
when end_read_upper=>
--fetch data
--if(dq_swap='0') then
if(dq_swap='0') then
Z3_DATA(31 downto 16) <= DQ;
--else
-- Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
--end if;
else
Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
if(DS1='1' and DS0='1')then -- no lower half
lan_rdy <='1';
LAN_SM <= end_read_upper; -- stay here until cylce end
@@ -378,11 +378,11 @@ begin
LAN_SM<=end_read_lower;
when end_read_lower=>
--fetch data
--if(dq_swap='0') then
if(dq_swap='0') then
Z3_DATA(15 downto 0) <= DQ;
--else
-- Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
--end if;
else
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
lan_rdy <='1';
LAN_SM<=end_read_lower; -- stay here until cylce end
when start_write_upper=>
@@ -394,11 +394,11 @@ begin
LAN_SM<=end_write_upper;
when end_write_upper=>
-- prepare the data for write
--if(dq_swap='0') then
if(dq_swap='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
--else
-- DQ_DATA(15 downto 0) <= Z3_DATA_IN(7 downto 0) & Z3_DATA_IN(15 downto 8);
--end if;
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN(7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
if(DS1='1' and DS0='1')then -- no lower half
lan_rdy <='1';