Byteswap working

This commit is contained in:
MHeinrichs
2018-12-18 00:00:58 +01:00
parent 8cbd5c7cef
commit 11a6adca8a
34 changed files with 12158 additions and 9568 deletions
+20 -18
View File
@@ -89,8 +89,6 @@ Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <beh
* HDL Analysis *
=========================================================================
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" line 291: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<LAN_SM_RST>
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
@@ -116,7 +114,6 @@ WARNING:Xst:647 - Input <CP_IRQ> is never used. This port will be preserved and
WARNING:Xst:2565 - Inout <A<1>> is never assigned.
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <C1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <dq_swap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <LAN_BASEADR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found finite state machine <FSM_0> for signal <LAN_SM>.
@@ -177,6 +174,8 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit register for signal <autoconfig>.
Found 8-bit register for signal <Dout1>.
Found 16-bit register for signal <DQ_DATA>.
Found 1-bit register for signal <dq_swap>.
Found 2-bit comparator less for signal <dq_swap$cmp_lt0000> created at line 248.
Found 14-bit register for signal <LAN_A_INIT>.
Found 1-bit register for signal <lan_adr>.
Found 1-bit register for signal <LAN_CS_RST>.
@@ -197,7 +196,8 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Summary:
inferred 2 Finite State Machine(s).
inferred 1 ROM(s).
inferred 47 D-type flip-flop(s).
inferred 48 D-type flip-flop(s).
inferred 1 Comparator(s).
inferred 57 Tristate(s).
Unit <LAN_IDE_CP> synthesized.
@@ -208,11 +208,13 @@ HDL Synthesis Report
Macro Statistics
# ROMs : 1
16x8-bit ROM : 1
# Registers : 53
1-bit register : 48
# Registers : 54
1-bit register : 49
14-bit register : 2
16-bit register : 2
8-bit register : 1
# Comparators : 1
2-bit comparator less : 1
# Tristates : 27
1-bit tristate buffer : 25
16-bit tristate buffer : 2
@@ -286,8 +288,8 @@ Macro Statistics
# FSMs : 2
# ROMs : 1
16x8-bit ROM : 1
# Registers : 47
Flip-Flops : 47
# Registers : 48
Flip-Flops : 48
=========================================================================
@@ -378,22 +380,22 @@ Design Statistics
# IOs : 116
Cell Usage :
# BELS : 599
# AND2 : 193
# AND3 : 18
# BELS : 779
# AND2 : 258
# AND3 : 34
# AND4 : 7
# AND8 : 3
# GND : 1
# INV : 189
# OR2 : 146
# INV : 239
# OR2 : 195
# OR3 : 22
# OR4 : 2
# OR8 : 16
# VCC : 1
# XOR2 : 1
# FlipFlops/Latches : 105
# FlipFlops/Latches : 106
# FD : 1
# FDC : 25
# FDC : 26
# FDCE : 3
# FDP : 42
# FDPE : 34
@@ -406,13 +408,13 @@ Cell Usage :
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.40 secs
Total CPU time to Xst completion: 8.29 secs
-->
Total memory usage is 4534752 kilobytes
Total memory usage is 4534748 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 54 ( 0 filtered)
Number of warnings : 52 ( 0 filtered)
Number of infos : 10 ( 0 filtered)