Dominick.Vansevenant/Zorro-LAN-IDE
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Combined Z2/Z3-Firmware

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The Z2/Z3-detection works now!
This commit is contained in:
MHeinrichs
2022-03-14 09:31:55 +01:00
parent 7444299170
commit 0f18ce181d
4 changed files with 1895 additions and 70 deletions
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Logic/LAN_IDE_V2/LAN_IDE_CP.vhd
+127 -70
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@@ -57,7 +57,7 @@ entity LAN_IDE_CP is
LDS : in STD_LOGIC;
AS : in STD_LOGIC;
RW : in STD_LOGIC;
Z3 : in STD_LOGIC;
Z3 : inout STD_LOGIC;
DS1 : in STD_LOGIC;
FCS : in STD_LOGIC;
RESET : in STD_LOGIC;
@@ -137,6 +137,14 @@ architecture Behavioral of LAN_IDE_CP is
signal LAN_RD_S: std_logic;
signal LAN_WRH_S: std_logic;
signal LAN_WRL_S: std_logic;
signal LAN_ACCESS_Z2: STD_LOGIC;
signal DQ_SWAP_Z2: STD_LOGIC;
signal LAN_INT_ENABLE_Z2: STD_LOGIC;
signal LAN_RD_S_Z2: STD_LOGIC;
signal LAN_WRH_S_Z2: STD_LOGIC;
signal LAN_WRL_S_Z2: STD_LOGIC;
signal LAN_READY: std_logic;
signal CONFIG_READY: std_logic;
signal LAN_IRQ_D0: std_logic;
@@ -159,6 +167,7 @@ architecture Behavioral of LAN_IDE_CP is
signal LAN_CS_RST: std_logic;
signal LAN_WR_RST: std_logic;
signal LAN_INIT_FINISHED: std_logic;
signal INT_VECTOR_CYCLE: std_logic;
signal LAN_A_INIT:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FFF";
@@ -192,7 +201,7 @@ begin
end if;
end process;
clock_init: process(reset,CLK_EXT)
clock_init: process(reset,AMIGA_CLK)
begin
if(reset='0')then
--default values
@@ -201,7 +210,8 @@ begin
LAN_RST_SM<=nop;
LAN_A_INIT<="11"&x"FFF";
LAN_D_INIT<= x"0000";
elsif(rising_edge(CLK_EXT))then --reset is high!
LAN_INIT_FINISHED <= '0';
elsif(rising_edge(AMIGA_CLK))then --reset is high!
case LAN_RST_SM is
when nop=>
LAN_CS_RST<='0';
@@ -247,7 +257,8 @@ begin
LAN_D_INIT <= LAN_D_SET;
when done=>
LAN_CS_RST<='0';
LAN_WR_RST<='0';
LAN_WR_RST<='0';
LAN_INIT_FINISHED <='1';
LAN_RST_SM<=done;
LAN_A_INIT <= LAN_A_SETREG;
LAN_D_INIT <= LAN_D_SET;
@@ -257,36 +268,27 @@ begin
ADDRESS_Z3_DECODE: process(FCS,reset)
begin
if(reset='0' )then
if(reset='0')then
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
DQ_SWAP <= '0';
Z3_ADR <= (others => '1');
INT_VECTOR_CYCLE <='0';
elsif(falling_edge(FCS))then
if(Z3='1') then
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
INT_VECTOR_CYCLE <= not MTCR; --is this s special int vector cycle?!?
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
--lan base
--if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
if((D(15 downto 8) ) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then --only the upper 8 bits matter!!!
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
LAN_ACCESS <= '1';
else
LAN_ACCESS <= '0';
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
INT_VECTOR_CYCLE <= not MTCR; --is this s special int vector cycle?!?
if((D(15 downto 8) ) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then --only the upper 8 bits matter!!!
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
LAN_ACCESS <= '1';
else
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
DQ_SWAP <= '0';
end if;
end if;
end process ADDRESS_Z3_DECODE;
@@ -297,22 +299,37 @@ begin
AUTOCONFIG_Z2_ACCESS <= '0';
IDE_ACCESS <= '0';
CP_ACCESS <= '0';
LAN_ACCESS_Z2 <= '0';
DQ_SWAP_Z2 <= '0';
elsif(rising_edge(AMIGA_CLK))then
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_Z2_DONE /= "111" and CFIN='0' and LAN_ACCESS = '0')then
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_Z2_DONE /= "111" and CFIN='0' )then
AUTOCONFIG_Z2_ACCESS <= '1';
else
AUTOCONFIG_Z2_ACCESS <= '0';
end if;
--LANz2-Base
if(A(23 downto 16) = LAN_BASEADR and SHUT_UP_Z2(0)='0' and Z3 ='0' )then
if(A(14 downto 13)<"11")then
DQ_SWAP_Z2 <= '1';
else
DQ_SWAP_Z2 <= '0';
end if;
LAN_ACCESS_Z2 <= '1';
else
LAN_ACCESS_Z2 <= '0';
DQ_SWAP_Z2 <= '0';
end if;
--CP base
if(A(23 downto 16) = CP_BASEADR and SHUT_UP_Z2(1)='0' and LAN_ACCESS = '0')then
if(A(23 downto 16) = CP_BASEADR and SHUT_UP_Z2(1)='0' )then
CP_ACCESS <= '1';
else
CP_ACCESS <= '0';
end if;
--IDE base
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP_Z2(2)='0' and LAN_ACCESS = '0')then
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP_Z2(2)='0' )then
IDE_ACCESS <= '1';
else
IDE_ACCESS <= '0';
@@ -350,7 +367,7 @@ begin
lan_rst_gen: process (CLK_EXT)
begin
if falling_edge(CLK_EXT) then
if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or INT_VECTOR_CYCLE ='1') then
if(FCS ='1' or reset = '0' or INT_VECTOR_CYCLE ='1' or Z3_DS = "1111" or LAN_ACCESS = '0') then
LAN_SM_RST <='1';
else
LAN_SM_RST <='0';
@@ -358,7 +375,7 @@ begin
end if;
end process lan_rst_gen;
--lan signal generation: all Signals are HIGH active!
--lan signal generation: all Signals are HIGH active!
lan_data_multiplex: process (CLK_EXT,reset)
begin
if(reset ='0' ) then
@@ -369,7 +386,14 @@ begin
-- so I have to move this out of the cycle start condition and prepare it for every loop
if(LAN_SM = nop) then
if(LAN_SM = end_write_upper)then
-- prepare the data for lower write
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
elsif(LAN_SM = nop)then
-- prepare the data for write
if(Z3_DS(3 downto 2) < "11")then
if(DQ_SWAP='0') then
@@ -384,19 +408,10 @@ begin
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
end if;
elsif(LAN_SM = end_write_upper)then
-- prepare the data for lower write
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
end if;
end if;
end process lan_data_multiplex;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
begin
@@ -418,16 +433,12 @@ begin
case LAN_SM is
when nop=>
--cycle start!
-- prepare the data for write
-- this is a quite complex thing for a cpld
-- so I have to move this out of the cycle start condition and prepare it for every loop
if(Z3_DS(3 downto 2) = "11")then
-- lower word!
Z3_A_LOW <= '1';
end if;
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
@@ -446,6 +457,7 @@ begin
LAN_SM <= start_write_lower;
end if;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
@@ -491,7 +503,9 @@ begin
LAN_SM <= wait_write_upper;
when wait_write_upper=>
LAN_SM<=end_write_upper;
when end_write_upper=>
when end_write_upper=>
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_write_upper; -- stay here until cylce end
@@ -525,7 +539,7 @@ begin
end process lan_rw_gen;
--autoconfig
autoconfig_proc: process (reset, CLK_EXT)
autoconfig_proc: process (reset, AMIGA_CLK)
begin
if reset = '0' then
-- reset active ...
@@ -536,7 +550,7 @@ begin
CP_BASEADR<=x"FF";
AUTO_CONFIG_Z2_DONE <="000";
LAN_BASEADR<=x"FF";
elsif rising_edge(CLK_EXT) then -- no reset, so wait for rising edge of the clock
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
D_Z2_OUT<="1111";
if(AS='1')then
AUTO_CONFIG_Z2_DONE <= AUTO_CONFIG_Z2_DONE or AUTO_CONFIG_Z2_DONE_CYCLE or (not IDE_OFF & "00") ;
@@ -544,7 +558,7 @@ begin
case A(6 downto 1) is
when "000000" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
D_Z2_OUT <= "1"&not(Z3)&"00" ; --ZII, No-System-Memory, no ROM
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "1100" ; --ZII, No-System-Memory, no ROM
else
@@ -604,17 +618,23 @@ begin
D_Z2_OUT <= "1110" ; --Rom vector low byte low nibble
when "100010" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
if(RW='0' )then
if(AUTO_CONFIG_Z2_DONE(0) = '0' and Z3 = '1')then
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress Z3
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
end if;
end if;
when "100100" =>
D_Z2_OUT <= "1111" ;
if(RW='0' and AUTO_CONFIG_Z2_DONE(0)='1')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
if(Z3 ='0')then
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress Z2
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
end if;
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(1) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
@@ -642,23 +662,59 @@ begin
end process autoconfig_proc; --- that's all
--lan signal generation: all Signals are HIGH active!
lan_rw_gen_Z2: process (AMIGA_CLK,reset)
begin
if(reset ='0') then
LAN_INT_ENABLE_Z2 <='0';
LAN_RD_S_Z2 <= '0';
LAN_WRH_S_Z2 <= '0';
LAN_WRL_S_Z2 <= '0';
elsif falling_edge(AMIGA_CLK) then
--default values
LAN_RD_S_Z2 <= '0';
LAN_WRH_S_Z2 <= '0';
LAN_WRL_S_Z2 <= '0';
LAN_CS <= LAN_ACCESS when reset='1' and Z3_ADR(15)='0' else LAN_CS_RST;
LAN_WRL <= LAN_WRL_S when FCS='0' and reset = '1' else LAN_WR_RST;
LAN_WRH <= LAN_WRH_S when FCS='0' and reset = '1' else LAN_WR_RST;
LAN_RD <= LAN_RD_S when FCS='0' and reset = '1' else '0';
if(LAN_ACCESS_Z2='1' and AS = '0' and DS='0' and A(15)='0')then
LAN_RD_S_Z2 <= RW;
-- swapped LDS/UDS here: ENC624 is little endian
LAN_WRH_S_Z2 <= not LDS and not RW;
LAN_WRL_S_Z2 <= not UDS and not RW;
end if;
if(LAN_ACCESS_Z2 = '1' and AS = '0' and DS ='0' and RW='0' and A(15)='1') then --enable if a write to A15 occured
LAN_INT_ENABLE_Z2 <= D(15);
end if;
end if;
end process lan_rw_gen_Z2;
LAN_CS <= LAN_CS_RST when LAN_INIT_FINISHED ='0' else
LAN_ACCESS_Z2 when Z3 = '0' else
LAN_ACCESS;
LAN_WRL <= LAN_WR_RST when LAN_INIT_FINISHED ='0' else
LAN_WRL_S_Z2 when AS='0' else
LAN_WRL_S;
LAN_WRH <= LAN_WR_RST when LAN_INIT_FINISHED ='0' else
LAN_WRH_S_Z2 when AS='0' else
LAN_WRH_S;
LAN_RD <= '0' when LAN_INIT_FINISHED ='0' else
LAN_RD_S_Z2 when AS='0' else
LAN_RD_S;
-- LAN_CFG <= "ZZZZ";
A_LAN(13 downto 0)<= LAN_A_INIT(13 downto 0) when LAN_RST_SM/=done else
A_LAN(13 downto 0)<= LAN_A_INIT(13 downto 0) when LAN_INIT_FINISHED ='0' else
Z3_ADR(14 downto 2) & Z3_A_LOW when LAN_ACCESS = '1' else
A(14 downto 1) when LAN_ACCESS_Z2 = '1' else
A(12 downto 1)&"00";
--signal assignment
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
D_Z2_OUT & x"FFF" when RW='1' and AS_D='0' and AUTOCONFIG_Z2_ACCESS ='1' else
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and CP_ACCESS = '1' and AS_D='0' else
DQ(15 downto 0) when RW='1' and IDE_ACCESS = '1' and AS_D='0' else
DQ(7 downto 0)&DQ(15 downto 8) when RW='1' and (CP_ACCESS = '1' or (LAN_ACCESS_Z2 ='1' and DQ_SWAP_Z2 ='1')) and AS_D='0' else
DQ(15 downto 0) when RW='1' and (IDE_ACCESS = '1' or (LAN_ACCESS_Z2 ='1' and DQ_SWAP_Z2 ='0')) and AS_D='0' else
(others => 'Z');
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
@@ -667,22 +723,22 @@ begin
A(7 downto 1) <= (others => 'Z');
--defined lancp signal that matches both LAN and CP addresses
DQ <= LAN_D_INIT when LAN_RST_SM/=done else
DQ <= LAN_D_INIT when LAN_INIT_FINISHED ='0' else
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and LAN_ACCESS ='1' else
D(15 downto 8 ) & D(15 downto 8) when RW='0' and AS='0' and CP_ACCESS ='1' else
D when RW='0' and AS='0' and IDE_ACCESS ='1' else
x"0000" when RW = '1' and AS= '0' and IDE_ACCESS ='1' and ROM_OE_S ='1' and IDE_R_S = '1' else --clear the bus just before an IDE-Read!
D(7 downto 0 ) & D(15 downto 8) when RW='0' and AS='0' and (CP_ACCESS ='1' or (LAN_ACCESS_Z2 ='1' and DQ_SWAP_Z2 ='1')) else
D when RW='0' and AS='0' and (IDE_ACCESS = '1' or (LAN_ACCESS_Z2 ='1' and DQ_SWAP_Z2 ='0')) else
x"0000" when RW = '1' and AS= '0' and AS_D ='1' and IDE_ACCESS ='1' else --clear the bus just before an IDE-Read!
(others => 'Z');
INT2_OUT <= '0' when LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1' else
INT2_OUT <= '0' when LAN_IRQ_OUT = '0' and (LAN_INT_ENABLE = '1' or LAN_INT_ENABLE_Z2 ='1') else
--'0' when CP_IRQ = '0' else
'Z';
INT6_OUT <= '0' when CP_IRQ = '0' else
'Z';
OWN <= 'Z';
SLAVE <= '0' when FCS='0' and LAN_ACCESS = '1' else
'0' when AS='0' and (AUTOCONFIG_Z2_ACCESS = '1' or IDE_ACCESS = '1' or CP_ACCESS = '1') else '1';
'0' when AS='0' and (AUTOCONFIG_Z2_ACCESS = '1' or IDE_ACCESS = '1' or CP_ACCESS = '1' or LAN_ACCESS_Z2 = '1') else '1';
CFOUT <= '0' when AUTO_CONFIG_Z2_DONE ="111" else '1';
OVR <= '0' when FCS='0' and LAN_ACCESS = '1' else 'Z'; --is Cache inhibit on Z3!
@@ -719,13 +775,14 @@ begin
end if;
end process ide_rw_gen;
IDE_W <= IDE_W_S when AS ='0' else '1';
IDE_R <= IDE_R_S when AS ='0' else '1';
ROM_OE<= ROM_OE_S when AS ='0' else '1';
IDE_R <= IDE_R_S when AS_D ='0' else '1';
ROM_OE<= ROM_OE_S when AS_D ='0' else '1';
IDE_CS(0)<= not(A(12));
IDE_CS(1)<= not(A(13));
IDE_A(2 downto 0) <= A(11 downto 9);
ROM_B <= "00";
Z3 <= '1' when reset ='0' else 'Z';
--cp signal generation
cp_rw_gen: process (AMIGA_CLK, reset)