Dominick.Vansevenant/Zorro-LAN-IDE
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MHeinrichs
2017-01-15 00:14:51 +01:00
parent f7b79faf13
commit 0a5cadccdc
202 changed files with 39331 additions and 13191 deletions
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Logic/LAN_IDE/LAN_IDE_CP.syr
+34 -38
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@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
Total CPU time to Xst completion: 0.09 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
Total CPU time to Xst completion: 0.09 secs
--> Reading design: LAN_IDE_CP.prj
@@ -45,7 +45,7 @@ Top Module Name : LAN_IDE_CP
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : Yes
Mux Extraction : Yes
Mux Extraction : No
Resource Sharing : YES
---- Target Options
@@ -55,10 +55,10 @@ XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 2
Optimization Goal : Area
Optimization Effort : 1
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
Netlist Hierarchy : Rebuilt
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
@@ -76,19 +76,18 @@ wysiwyg : NO
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work.
Entity <LAN_IDE_CP> compiled.
Entity <LAN_IDE_CP> (Architecture <Behavioral>) compiled.
Architecture behavioral of Entity lan_ide_cp is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <Behavioral>).
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <Behavioral>).
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" line 131: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<AS>
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
@@ -106,9 +105,12 @@ WARNING:Xst:647 - Input <DS0> is never used. This port will be preserved and lef
WARNING:Xst:647 - Input <DS1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <MTACK> is never assigned.
WARNING:Xst:647 - Input <LAN_INT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_IRQ> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Z3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CLK_EXT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <LAN_INT_ENABLE> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <LAN_INT_D0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Found 16-bit tristate buffer for signal <D>.
@@ -141,21 +143,19 @@ WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected
Found 1-bit register for signal <lan>.
Found 8-bit comparator equal for signal <lan$cmp_eq0000> created at line 140.
Found 8-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_INT_ENABLE>.
Found 1-bit register for signal <LAN_RD_S>.
Found 1-bit register for signal <LAN_WRH_S>.
Found 1-bit register for signal <LAN_WRL_S>.
Found 1-bit register for signal <ROM_OE_S>.
Found 3-bit register for signal <SHUT_UP>.
Summary:
inferred 6 D-type flip-flop(s).
inferred 5 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
inferred 5 Comparator(s).
inferred 1 Xor(s).
inferred 40 Tristate(s).
Unit <LAN_IDE_CP> synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
=========================================================================
HDL Synthesis Report
@@ -163,8 +163,8 @@ HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
2-bit adder : 1
# Registers : 24
1-bit register : 18
# Registers : 23
1-bit register : 17
2-bit register : 2
4-bit register : 1
8-bit register : 3
@@ -190,8 +190,8 @@ Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
2-bit adder : 1
# Registers : 6
Flip-Flops : 6
# Registers : 5
Flip-Flops : 5
# Comparators : 3
8-bit comparator equal : 3
@@ -221,7 +221,7 @@ Final Results
RTL Top Level Output File Name : LAN_IDE_CP.ngr
Top Level Output File Name : LAN_IDE_CP
Output Format : NGC
Optimization Goal : Speed
Optimization Goal : Area
Keep Hierarchy : Yes
Target Technology : XC9500XL CPLDs
Macro Preserve : YES
@@ -233,39 +233,35 @@ Design Statistics
# IOs : 116
Cell Usage :
# BELS : 457
# AND2 : 106
# AND3 : 15
# AND4 : 9
# AND5 : 1
# AND8 : 3
# BELS : 414
# AND2 : 97
# AND3 : 9
# GND : 1
# INV : 197
# OR2 : 87
# OR3 : 7
# OR4 : 4
# VCC : 1
# INV : 153
# OR2 : 120
# OR3 : 5
# OR4 : 3
# XOR2 : 26
# FlipFlops/Latches : 50
# FlipFlops/Latches : 49
# FD : 9
# FDC : 4
# FDCE : 37
# IO Buffers : 109
# IBUF : 36
# FDCE : 36
# IO Buffers : 106
# IBUF : 33
# IOBUFE : 32
# OBUF : 33
# OBUFE : 8
=========================================================================
Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 8.25 secs
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.55 secs
-->
Total memory usage is 290008 kilobytes
Total memory usage is 293716 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 10 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
Number of warnings : 13 ( 0 filtered)
Number of infos : 0 ( 0 filtered)