Timing Report

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Design Name LAN_IDE_CP
Device, Speed (SpeedFile Version) XC95288XL, -10 (3.0)
Date Created Sun Jan 21 23:54:29 2018
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE<1>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE<0>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<0>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<1>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_INT_ENABLE.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<0>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<1>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<2>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<3>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<4>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<5>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<6>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<7>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'Dout1<0>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'Dout1<1>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'Dout1<2>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'Dout1<3>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<0>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<1>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<2>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<3>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<4>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<5>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<6>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<7>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<0>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<1>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<2>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<3>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<4>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<5>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<6>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<7>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_IRQ_OUT.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_ENABLE.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'DS_D.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_IRQ_D0.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'SHUT_UP<0>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'SHUT_UP<1>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'SHUT_UP<2>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_R_S.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_W_S.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'ROM_OE_S.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'CP_WE_S.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'CP_RD_S.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'CP_WE_QUIRK.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_RD_S.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_WRH_S.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'LAN_WRL_S.CLKF' has multiple original clock nets 'C3' 'C1'.

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for AS
Clock to Setup (tCYC) 11.400 ns.
Pad to Pad Delay (tPD) 18.700 ns.
Setup to Clock at the Pad (tSU) 12.600 ns.
Clock Pad to Output Pad Delay (tCO) 34.300 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS_CLK_EXT 30.3 11.0 12 0
TS_C3 333.3 11.4 135 0
TS_C1 333.3 0.0 0 0


Constraint: TS_CLK_EXT

Description: PERIOD:CLK_EXT:30.303nS:HIGH:15.151nS
Path Requirement (ns) Delay (ns) Slack (ns)
LAN_RST_SM_FSM_FFd2.Q to LAN_WR_RST.D 30.300 11.000 19.300
LAN_RST_SM_FSM_FFd3.Q to LAN_WR_RST.D 30.300 11.000 19.300
LAN_RST_SM_FSM_FFd1.Q to LAN_RST_SM_FSM_FFd1.D 30.300 10.000 20.300


Constraint: TS_C3

Description: PERIOD:C3:333.333nS:HIGH:166.666nS
Path Requirement (ns) Delay (ns) Slack (ns)
AUTO_CONFIG_DONE<0>.Q to Dout1<0>.D 333.300 11.400 321.900
AUTO_CONFIG_DONE<0>.Q to Dout1<1>.D 333.300 11.400 321.900
AUTO_CONFIG_DONE<0>.Q to Dout1<2>.D 333.300 11.400 321.900


Constraint: TS_C1

Description: PERIOD:C1:333.333nS:HIGH:166.666nS
Path Requirement (ns) Delay (ns) Slack (ns)



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK_EXT 90.909 Limited by Cycle Time for CLK_EXT
AS 71.429 Limited by Clock Pulse Width for AS
C3 71.429 Limited by Clock Pulse Width for C3
C1 71.429 Limited by Clock Pulse Width for C1

Setup/Hold Times for Clocks

Setup/Hold Times for Clock CLK_EXT
Source Pad Setup to clk (edge) Hold to clk (edge)
RESET 7.500 0.000

Setup/Hold Times for Clock AS
Source Pad Setup to clk (edge) Hold to clk (edge)
A<13> 3.500 0.000
A<14> 3.500 0.000
A<16> 12.200 1.400
A<17> 12.200 1.400
A<18> 12.600 1.400
A<19> 12.200 1.400
A<20> 12.600 1.400
A<21> 12.200 1.400
A<22> 12.200 1.400
A<23> 12.200 1.400
CFIN 11.200 1.400

Setup/Hold Times for Clock C3
Source Pad Setup to clk (edge) Hold to clk (edge)
A<15> -4.600 9.100
A<1> -4.200 9.100
A<2> -4.200 9.100
A<3> -4.200 9.100
A<4> -4.200 9.100
A<5> -4.200 9.100
A<6> -4.200 9.100
AS -4.200 9.100
D<10> -5.600 9.100
D<11> -4.600 9.100
D<12> -4.600 9.100
D<13> -5.600 9.100
D<14> -4.600 9.100
D<15> -5.600 9.100
D<8> -5.600 9.100
D<9> -5.600 9.100
LAN_INT -4.600 9.100
LDS -4.200 9.100
RESET -5.600 9.100
RW -4.600 9.100
UDS -4.200 9.100

Setup/Hold Times for Clock C1
Source Pad Setup to clk (edge) Hold to clk (edge)
A<15> -4.600 9.100
A<1> -4.200 9.100
A<2> -4.200 9.100
A<3> -4.200 9.100
A<4> -4.200 9.100
A<5> -4.200 9.100
A<6> -4.200 9.100
AS -4.200 9.100
D<10> -5.600 9.100
D<11> -4.600 9.100
D<12> -4.600 9.100
D<13> -5.600 9.100
D<14> -4.600 9.100
D<15> -5.600 9.100
D<8> -5.600 9.100
D<9> -5.600 9.100
LAN_INT -4.600 9.100
LDS -4.200 9.100
RESET -5.600 9.100
RW -4.600 9.100
UDS -4.200 9.100


Clock to Pad Timing

Clock CLK_EXT to Pad
Destination Pad Clock (edge) to Pad
DQ<0> 22.200
DQ<10> 22.200
DQ<11> 22.200
DQ<12> 22.200
DQ<13> 22.200
DQ<14> 22.200
DQ<15> 22.200
DQ<1> 22.200
DQ<2> 22.200
DQ<3> 22.200
DQ<4> 22.200
DQ<5> 22.200
DQ<6> 22.200
DQ<7> 22.200
DQ<8> 22.200
DQ<9> 22.200
A_LAN<0> 13.500
A_LAN<10> 13.500
A_LAN<11> 13.500
A_LAN<12> 13.500
A_LAN<13> 13.500
A_LAN<1> 13.500
A_LAN<2> 13.500
A_LAN<3> 13.500
A_LAN<4> 13.500
A_LAN<5> 13.500
A_LAN<6> 13.500
A_LAN<7> 13.500
A_LAN<8> 13.500
A_LAN<9> 13.500
LAN_CS 13.500
LAN_WRH 13.500
LAN_WRL 13.500

Clock AS to Pad
Destination Pad Clock (edge) to Pad
D<0> 26.600
D<10> 26.600
D<11> 26.600
D<12> 26.600
D<13> 26.600
D<14> 26.600
D<15> 26.600
D<1> 26.600
D<2> 26.600
D<3> 26.600
D<4> 26.600
D<5> 26.600
D<6> 26.600
D<7> 26.600
D<8> 26.600
D<9> 26.600
DQ<0> 26.600
DQ<10> 26.600
DQ<11> 26.600
DQ<12> 26.600
DQ<13> 26.600
DQ<14> 26.600
DQ<15> 26.600
DQ<1> 26.600
DQ<2> 26.600
DQ<3> 26.600
DQ<4> 26.600
DQ<5> 26.600
DQ<6> 26.600
DQ<7> 26.600
DQ<8> 26.600
DQ<9> 26.600
DTACK 18.900
OVR 18.900
A_LAN<2> 17.900
A_LAN<3> 17.900
A_LAN<4> 17.900
A_LAN<5> 17.900
LAN_CS 17.900
SLAVE 17.900
CP_CS 10.200

Clock C3 to Pad
Destination Pad Clock (edge) to Pad
INT_OUT 34.300
CFOUT 26.600
CP_RD 26.600
D<13> 26.600
D<15> 26.600
CP_WE 25.600
D<12> 25.600
D<14> 25.600
IDE_R 25.600
IDE_W 25.600
LAN_RD 25.600
LAN_WRH 25.600
LAN_WRL 25.600
ROM_OE 25.600

Clock C1 to Pad
Destination Pad Clock (edge) to Pad
INT_OUT 34.300
CFOUT 26.600
CP_RD 26.600
D<13> 26.600
D<15> 26.600
CP_WE 25.600
D<12> 25.600
D<14> 25.600
IDE_R 25.600
IDE_W 25.600
LAN_RD 25.600
LAN_WRH 25.600
LAN_WRL 25.600
ROM_OE 25.600


Clock to Setup Times for Clocks

Clock to Setup for clock CLK_EXT
Source Destination Delay
LAN_RST_SM_FSM_FFd2.Q LAN_WR_RST.D 11.000
LAN_RST_SM_FSM_FFd3.Q LAN_WR_RST.D 11.000
LAN_RST_SM_FSM_FFd1.Q LAN_RST_SM_FSM_FFd1.D 10.000
LAN_RST_SM_FSM_FFd1.Q LAN_RST_SM_FSM_FFd2.D 10.000
LAN_RST_SM_FSM_FFd1.Q LAN_RST_SM_FSM_FFd3.D 10.000
LAN_RST_SM_FSM_FFd2.Q LAN_CS_RST.D 10.000
LAN_RST_SM_FSM_FFd2.Q LAN_RST_SM_FSM_FFd1.D 10.000
LAN_RST_SM_FSM_FFd2.Q LAN_RST_SM_FSM_FFd2.D 10.000
LAN_RST_SM_FSM_FFd2.Q LAN_RST_SM_FSM_FFd3.D 10.000
LAN_RST_SM_FSM_FFd3.Q LAN_CS_RST.D 10.000
LAN_RST_SM_FSM_FFd3.Q LAN_RST_SM_FSM_FFd1.D 10.000
LAN_RST_SM_FSM_FFd3.Q LAN_RST_SM_FSM_FFd2.D 10.000

Clock to Setup for clock C3
Source Destination Delay
AUTO_CONFIG_DONE<0>.Q Dout1<0>.D 11.400
AUTO_CONFIG_DONE<0>.Q Dout1<1>.D 11.400
AUTO_CONFIG_DONE<0>.Q Dout1<2>.D 11.400
AUTO_CONFIG_DONE<1>.Q Dout1<0>.D 11.400
AUTO_CONFIG_DONE<1>.Q Dout1<1>.D 11.400
AUTO_CONFIG_DONE<1>.Q Dout1<2>.D 11.400
AUTO_CONFIG_DONE<0>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<1>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
AUTO_CONFIG_DONE<1>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<1>.Q Dout1<3>.D 11.000
AUTO_CONFIG_DONE_CYCLE<0>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
CP_BASEADR<3>.Q CP_BASEADR<3>.D 11.000
CP_BASEADR<4>.Q CP_BASEADR<4>.D 11.000
DS_D.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
DS_D.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
DS_D.Q CP_BASEADR<3>.D 11.000
DS_D.Q CP_BASEADR<4>.D 11.000
Dout1<0>.Q Dout1<0>.D 11.000
Dout1<3>.Q Dout1<3>.D 11.000
LAN_INT_ENABLE.Q LAN_IRQ_OUT.D 11.000
LAN_IRQ_D0.Q LAN_IRQ_OUT.D 11.000
AUTO_CONFIG_DONE<0>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<1>.D 10.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<2>.D 10.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<5>.D 10.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<6>.D 10.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<7>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<1>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<2>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<3>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<4>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<5>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<6>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<7>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<1>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<2>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<3>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<4>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<5>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<6>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<7>.D 10.000
AUTO_CONFIG_DONE<0>.Q SHUT_UP<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q SHUT_UP<1>.D 10.000
AUTO_CONFIG_DONE<0>.Q SHUT_UP<2>.D 10.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<0>.D 10.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<1>.D 10.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<2>.D 10.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<5>.D 10.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<6>.D 10.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<7>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<0>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<1>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<2>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<3>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<4>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<5>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<6>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<7>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<0>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<1>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<2>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<3>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<4>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<5>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<6>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<7>.D 10.000
AUTO_CONFIG_DONE<1>.Q SHUT_UP<0>.D 10.000
AUTO_CONFIG_DONE<1>.Q SHUT_UP<1>.D 10.000
AUTO_CONFIG_DONE<1>.Q SHUT_UP<2>.D 10.000
AUTO_CONFIG_DONE_CYCLE<0>.Q AUTO_CONFIG_DONE<0>.D 10.000
AUTO_CONFIG_DONE_CYCLE<1>.Q AUTO_CONFIG_DONE<1>.D 10.000
CP_BASEADR<0>.Q CP_BASEADR<0>.D 10.000
CP_BASEADR<1>.Q CP_BASEADR<1>.D 10.000
CP_BASEADR<2>.Q CP_BASEADR<2>.D 10.000
CP_BASEADR<5>.Q CP_BASEADR<5>.D 10.000
CP_BASEADR<6>.Q CP_BASEADR<6>.D 10.000
CP_BASEADR<7>.Q CP_BASEADR<7>.D 10.000
CP_WE_S.Q CP_WE_QUIRK.D 10.000
DS_D.Q CP_BASEADR<0>.D 10.000
DS_D.Q CP_BASEADR<1>.D 10.000
DS_D.Q CP_BASEADR<2>.D 10.000
DS_D.Q CP_BASEADR<5>.D 10.000
DS_D.Q CP_BASEADR<6>.D 10.000
DS_D.Q CP_BASEADR<7>.D 10.000
DS_D.Q IDE_BASEADR<0>.D 10.000
DS_D.Q IDE_BASEADR<1>.D 10.000
DS_D.Q IDE_BASEADR<2>.D 10.000
DS_D.Q IDE_BASEADR<3>.D 10.000
DS_D.Q IDE_BASEADR<4>.D 10.000
DS_D.Q IDE_BASEADR<5>.D 10.000
DS_D.Q IDE_BASEADR<6>.D 10.000
DS_D.Q IDE_BASEADR<7>.D 10.000
DS_D.Q LAN_BASEADR<0>.D 10.000
DS_D.Q LAN_BASEADR<1>.D 10.000
DS_D.Q LAN_BASEADR<2>.D 10.000
DS_D.Q LAN_BASEADR<3>.D 10.000
DS_D.Q LAN_BASEADR<4>.D 10.000
DS_D.Q LAN_BASEADR<5>.D 10.000
DS_D.Q LAN_BASEADR<6>.D 10.000
DS_D.Q LAN_BASEADR<7>.D 10.000
DS_D.Q SHUT_UP<0>.D 10.000
DS_D.Q SHUT_UP<1>.D 10.000
DS_D.Q SHUT_UP<2>.D 10.000
Dout1<1>.Q Dout1<1>.D 10.000
Dout1<2>.Q Dout1<2>.D 10.000
IDE_BASEADR<0>.Q IDE_BASEADR<0>.D 10.000
IDE_BASEADR<1>.Q IDE_BASEADR<1>.D 10.000
IDE_BASEADR<2>.Q IDE_BASEADR<2>.D 10.000
IDE_BASEADR<3>.Q IDE_BASEADR<3>.D 10.000
IDE_BASEADR<4>.Q IDE_BASEADR<4>.D 10.000
IDE_BASEADR<5>.Q IDE_BASEADR<5>.D 10.000
IDE_BASEADR<6>.Q IDE_BASEADR<6>.D 10.000
IDE_BASEADR<7>.Q IDE_BASEADR<7>.D 10.000
IDE_ENABLE.Q IDE_R_S.D 10.000
IDE_ENABLE.Q ROM_OE_S.D 10.000
LAN_BASEADR<0>.Q LAN_BASEADR<0>.D 10.000
LAN_BASEADR<1>.Q LAN_BASEADR<1>.D 10.000
LAN_BASEADR<2>.Q LAN_BASEADR<2>.D 10.000
LAN_BASEADR<3>.Q LAN_BASEADR<3>.D 10.000
LAN_BASEADR<4>.Q LAN_BASEADR<4>.D 10.000
LAN_BASEADR<5>.Q LAN_BASEADR<5>.D 10.000
LAN_BASEADR<6>.Q LAN_BASEADR<6>.D 10.000
LAN_BASEADR<7>.Q LAN_BASEADR<7>.D 10.000
LAN_INT_ENABLE.Q LAN_INT_ENABLE.D 10.000
LAN_IRQ_OUT.Q LAN_IRQ_OUT.D 10.000
SHUT_UP<0>.Q SHUT_UP<0>.D 10.000
SHUT_UP<1>.Q SHUT_UP<1>.D 10.000
SHUT_UP<2>.Q SHUT_UP<2>.D 10.000

Clock to Setup for clock C1
Source Destination Delay
AUTO_CONFIG_DONE<0>.Q Dout1<0>.D 11.400
AUTO_CONFIG_DONE<0>.Q Dout1<1>.D 11.400
AUTO_CONFIG_DONE<0>.Q Dout1<2>.D 11.400
AUTO_CONFIG_DONE<1>.Q Dout1<0>.D 11.400
AUTO_CONFIG_DONE<1>.Q Dout1<1>.D 11.400
AUTO_CONFIG_DONE<1>.Q Dout1<2>.D 11.400
AUTO_CONFIG_DONE<0>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<1>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
AUTO_CONFIG_DONE<1>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<1>.Q Dout1<3>.D 11.000
AUTO_CONFIG_DONE_CYCLE<0>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
CP_BASEADR<3>.Q CP_BASEADR<3>.D 11.000
CP_BASEADR<4>.Q CP_BASEADR<4>.D 11.000
DS_D.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
DS_D.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
DS_D.Q CP_BASEADR<3>.D 11.000
DS_D.Q CP_BASEADR<4>.D 11.000
Dout1<0>.Q Dout1<0>.D 11.000
Dout1<3>.Q Dout1<3>.D 11.000
LAN_INT_ENABLE.Q LAN_IRQ_OUT.D 11.000
LAN_IRQ_D0.Q LAN_IRQ_OUT.D 11.000
AUTO_CONFIG_DONE<0>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<1>.D 10.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<2>.D 10.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<5>.D 10.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<6>.D 10.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<7>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<1>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<2>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<3>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<4>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<5>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<6>.D 10.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<7>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<1>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<2>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<3>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<4>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<5>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<6>.D 10.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<7>.D 10.000
AUTO_CONFIG_DONE<0>.Q SHUT_UP<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q SHUT_UP<1>.D 10.000
AUTO_CONFIG_DONE<0>.Q SHUT_UP<2>.D 10.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<0>.D 10.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<1>.D 10.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<2>.D 10.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<5>.D 10.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<6>.D 10.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<7>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<0>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<1>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<2>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<3>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<4>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<5>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<6>.D 10.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<7>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<0>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<1>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<2>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<3>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<4>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<5>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<6>.D 10.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<7>.D 10.000
AUTO_CONFIG_DONE<1>.Q SHUT_UP<0>.D 10.000
AUTO_CONFIG_DONE<1>.Q SHUT_UP<1>.D 10.000
AUTO_CONFIG_DONE<1>.Q SHUT_UP<2>.D 10.000
AUTO_CONFIG_DONE_CYCLE<0>.Q AUTO_CONFIG_DONE<0>.D 10.000
AUTO_CONFIG_DONE_CYCLE<1>.Q AUTO_CONFIG_DONE<1>.D 10.000
CP_BASEADR<0>.Q CP_BASEADR<0>.D 10.000
CP_BASEADR<1>.Q CP_BASEADR<1>.D 10.000
CP_BASEADR<2>.Q CP_BASEADR<2>.D 10.000
CP_BASEADR<5>.Q CP_BASEADR<5>.D 10.000
CP_BASEADR<6>.Q CP_BASEADR<6>.D 10.000
CP_BASEADR<7>.Q CP_BASEADR<7>.D 10.000
CP_WE_S.Q CP_WE_QUIRK.D 10.000
DS_D.Q CP_BASEADR<0>.D 10.000
DS_D.Q CP_BASEADR<1>.D 10.000
DS_D.Q CP_BASEADR<2>.D 10.000
DS_D.Q CP_BASEADR<5>.D 10.000
DS_D.Q CP_BASEADR<6>.D 10.000
DS_D.Q CP_BASEADR<7>.D 10.000
DS_D.Q IDE_BASEADR<0>.D 10.000
DS_D.Q IDE_BASEADR<1>.D 10.000
DS_D.Q IDE_BASEADR<2>.D 10.000
DS_D.Q IDE_BASEADR<3>.D 10.000
DS_D.Q IDE_BASEADR<4>.D 10.000
DS_D.Q IDE_BASEADR<5>.D 10.000
DS_D.Q IDE_BASEADR<6>.D 10.000
DS_D.Q IDE_BASEADR<7>.D 10.000
DS_D.Q LAN_BASEADR<0>.D 10.000
DS_D.Q LAN_BASEADR<1>.D 10.000
DS_D.Q LAN_BASEADR<2>.D 10.000
DS_D.Q LAN_BASEADR<3>.D 10.000
DS_D.Q LAN_BASEADR<4>.D 10.000
DS_D.Q LAN_BASEADR<5>.D 10.000
DS_D.Q LAN_BASEADR<6>.D 10.000
DS_D.Q LAN_BASEADR<7>.D 10.000
DS_D.Q SHUT_UP<0>.D 10.000
DS_D.Q SHUT_UP<1>.D 10.000
DS_D.Q SHUT_UP<2>.D 10.000
Dout1<1>.Q Dout1<1>.D 10.000
Dout1<2>.Q Dout1<2>.D 10.000
IDE_BASEADR<0>.Q IDE_BASEADR<0>.D 10.000
IDE_BASEADR<1>.Q IDE_BASEADR<1>.D 10.000
IDE_BASEADR<2>.Q IDE_BASEADR<2>.D 10.000
IDE_BASEADR<3>.Q IDE_BASEADR<3>.D 10.000
IDE_BASEADR<4>.Q IDE_BASEADR<4>.D 10.000
IDE_BASEADR<5>.Q IDE_BASEADR<5>.D 10.000
IDE_BASEADR<6>.Q IDE_BASEADR<6>.D 10.000
IDE_BASEADR<7>.Q IDE_BASEADR<7>.D 10.000
IDE_ENABLE.Q IDE_R_S.D 10.000
IDE_ENABLE.Q ROM_OE_S.D 10.000
LAN_BASEADR<0>.Q LAN_BASEADR<0>.D 10.000
LAN_BASEADR<1>.Q LAN_BASEADR<1>.D 10.000
LAN_BASEADR<2>.Q LAN_BASEADR<2>.D 10.000
LAN_BASEADR<3>.Q LAN_BASEADR<3>.D 10.000
LAN_BASEADR<4>.Q LAN_BASEADR<4>.D 10.000
LAN_BASEADR<5>.Q LAN_BASEADR<5>.D 10.000
LAN_BASEADR<6>.Q LAN_BASEADR<6>.D 10.000
LAN_BASEADR<7>.Q LAN_BASEADR<7>.D 10.000
LAN_INT_ENABLE.Q LAN_INT_ENABLE.D 10.000
LAN_IRQ_OUT.Q LAN_IRQ_OUT.D 10.000
SHUT_UP<0>.Q SHUT_UP<0>.D 10.000
SHUT_UP<1>.Q SHUT_UP<1>.D 10.000
SHUT_UP<2>.Q SHUT_UP<2>.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
AS D<0> 18.700
AS D<10> 18.700
AS D<11> 18.700
AS D<12> 18.700
AS D<13> 18.700
AS D<14> 18.700
AS D<15> 18.700
AS D<1> 18.700
AS D<2> 18.700
AS D<3> 18.700
AS D<4> 18.700
AS D<5> 18.700
AS D<6> 18.700
AS D<7> 18.700
AS D<8> 18.700
AS D<9> 18.700
AS DQ<0> 18.700
AS DQ<10> 18.700
AS DQ<11> 18.700
AS DQ<12> 18.700
AS DQ<13> 18.700
AS DQ<14> 18.700
AS DQ<15> 18.700
AS DQ<1> 18.700
AS DQ<2> 18.700
AS DQ<3> 18.700
AS DQ<4> 18.700
AS DQ<5> 18.700
AS DQ<6> 18.700
AS DQ<7> 18.700
AS DQ<8> 18.700
AS DQ<9> 18.700
CP_IRQ INT_OUT 18.700
D<0> DQ<8> 18.700
LDS DQ<0> 18.700
LDS DQ<10> 18.700
LDS DQ<11> 18.700
LDS DQ<12> 18.700
LDS DQ<13> 18.700
LDS DQ<14> 18.700
LDS DQ<15> 18.700
LDS DQ<1> 18.700
LDS DQ<2> 18.700
LDS DQ<3> 18.700
LDS DQ<4> 18.700
LDS DQ<5> 18.700
LDS DQ<6> 18.700
LDS DQ<7> 18.700
LDS DQ<8> 18.700
LDS DQ<9> 18.700
RW D<0> 18.700
RW D<10> 18.700
RW D<11> 18.700
RW D<12> 18.700
RW D<13> 18.700
RW D<14> 18.700
RW D<15> 18.700
RW D<1> 18.700
RW D<2> 18.700
RW D<3> 18.700
RW D<4> 18.700
RW D<5> 18.700
RW D<6> 18.700
RW D<7> 18.700
RW D<8> 18.700
RW D<9> 18.700
RW DQ<0> 18.700
RW DQ<10> 18.700
RW DQ<11> 18.700
RW DQ<12> 18.700
RW DQ<13> 18.700
RW DQ<14> 18.700
RW DQ<15> 18.700
RW DQ<1> 18.700
RW DQ<2> 18.700
RW DQ<3> 18.700
RW DQ<4> 18.700
RW DQ<5> 18.700
RW DQ<6> 18.700
RW DQ<7> 18.700
RW DQ<8> 18.700
RW DQ<9> 18.700
UDS DQ<0> 18.700
UDS DQ<10> 18.700
UDS DQ<11> 18.700
UDS DQ<12> 18.700
UDS DQ<13> 18.700
UDS DQ<14> 18.700
UDS DQ<15> 18.700
UDS DQ<1> 18.700
UDS DQ<2> 18.700
UDS DQ<3> 18.700
UDS DQ<4> 18.700
UDS DQ<5> 18.700
UDS DQ<6> 18.700
UDS DQ<7> 18.700
UDS DQ<8> 18.700
UDS DQ<9> 18.700
D<8> DQ<8> 15.200
D<1> DQ<1> 11.400
D<3> DQ<3> 11.400
AS CP_RD 11.000
AS DTACK 11.000
AS OVR 11.000
D<2> DQ<2> 11.000
D<4> DQ<4> 11.000
D<5> DQ<5> 11.000
D<6> DQ<14> 11.000
D<7> DQ<7> 11.000
DQ<12> D<12> 11.000
DQ<13> D<13> 11.000
DQ<14> D<14> 11.000
DQ<15> D<15> 11.000
DQ<4> D<12> 11.000
DQ<5> D<13> 11.000
DQ<6> D<14> 11.000
DQ<7> D<15> 11.000
DQ<8> D<8> 11.000
IDE_WAIT DTACK 11.000
A<10> A_LAN<9> 10.000
A<10> IDE_A<1> 10.000
A<11> A_LAN<10> 10.000
A<11> IDE_A<2> 10.000
A<12> A_LAN<11> 10.000
A<12> IDE_CS<0> 10.000
A<13> A_LAN<12> 10.000
A<13> IDE_CS<1> 10.000
A<14> A_LAN<13> 10.000
A<1> A_LAN<0> 10.000
A<2> A_LAN<1> 10.000
A<2> A_LAN<2> 10.000
A<3> A_LAN<2> 10.000
A<3> A_LAN<3> 10.000
A<4> A_LAN<3> 10.000
A<4> A_LAN<4> 10.000
A<5> A_LAN<4> 10.000
A<5> A_LAN<5> 10.000
A<6> A_LAN<5> 10.000
A<7> A_LAN<6> 10.000
A<8> A_LAN<7> 10.000
A<9> A_LAN<8> 10.000
A<9> IDE_A<0> 10.000
AS CP_WE 10.000
AS IDE_R 10.000
AS IDE_W 10.000
AS LAN_RD 10.000
AS LAN_WRH 10.000
AS LAN_WRL 10.000
AS ROM_OE 10.000
AS SLAVE 10.000
AUTOBOOT_OFF ROM_OE 10.000
DQ<0> D<0> 10.000
DQ<0> D<8> 10.000
DQ<10> D<10> 10.000
DQ<10> D<2> 10.000
DQ<11> D<11> 10.000
DQ<11> D<3> 10.000
DQ<12> D<4> 10.000
DQ<13> D<5> 10.000
DQ<15> D<7> 10.000
DQ<1> D<9> 10.000
DQ<2> D<10> 10.000
DQ<3> D<11> 10.000
DQ<6> D<6> 10.000
DQ<9> D<1> 10.000
DQ<9> D<9> 10.000
RESET LAN_CS 10.000
RESET LAN_RD 10.000
RESET LAN_WRH 10.000
RESET LAN_WRL 10.000
D<2> DQ<10> 7.900
D<3> DQ<11> 7.900
D<6> DQ<6> 7.900
D<0> DQ<0> 7.500
D<10> DQ<10> 7.500
D<10> DQ<2> 7.500
D<11> DQ<11> 7.500
D<11> DQ<3> 7.500
D<12> DQ<12> 7.500
D<12> DQ<4> 7.500
D<13> DQ<13> 7.500
D<13> DQ<5> 7.500
D<14> DQ<14> 7.500
D<14> DQ<6> 7.500
D<15> DQ<15> 7.500
D<15> DQ<7> 7.500
D<1> DQ<9> 7.500
D<4> DQ<12> 7.500
D<5> DQ<13> 7.500
D<7> DQ<15> 7.500
D<8> DQ<0> 7.500
D<9> DQ<1> 7.500
D<9> DQ<9> 7.500
DQ<14> D<6> 6.500
DQ<1> D<1> 6.500
DQ<2> D<2> 6.500
DQ<3> D<3> 6.500
DQ<4> D<4> 6.500
DQ<5> D<5> 6.500
DQ<7> D<7> 6.500
DQ<8> D<0> 6.500


Number of paths analyzed: 147
Number of Timing errors: 0
Analysis Completed: Sun Jan 21 23:54:29 2018