Timing Report

Need help reading this report?

Design Name LAN_IDE_CP
Device, Speed (SpeedFile Version) XC95288XL, -10 (3.0)
Date Created Sat Jan 14 23:47:44 2017
Created By Timing Report Generator: version P.68d
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE<0>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<0>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'SHUT_UP<0>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'SHUT_UP<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'SHUT_UP<2>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_ENABLE.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'CP_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'Dout1<0>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'Dout1<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'Dout1<2>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'Dout1<3>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'LAN_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'DS_D.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'CP_RD_S.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'CP_WE_S.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_R_S.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_W_S.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'LAN_RD_S.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'LAN_WRH_S.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'LAN_WRL_S.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'ROM_OE_S.CLKF' has multiple original clock nets 'C1' 'C3'.

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for C1
Clock to Setup (tCYC) 11.400 ns.
Pad to Pad Delay (tPD) 18.700 ns.
Setup to Clock at the Pad (tSU) 3.500 ns.
Clock Pad to Output Pad Delay (tCO) 26.600 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
AUTO_TS_F2F 0.0 11.4 208 208
AUTO_TS_P2P 0.0 26.6 224 224
AUTO_TS_P2F 0.0 13.9 544 544
AUTO_TS_F2P 0.0 20.4 106 106


Constraint: TS1000

Description: PERIOD:PERIOD_C1:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_C3:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_AS:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
AUTO_CONFIG_DONE<0>.Q to Dout1<0>.D 0.000 11.400 -11.400
AUTO_CONFIG_DONE<1>.Q to Dout1<0>.D 0.000 11.400 -11.400
AUTO_CONFIG_DONE<1>.Q to Dout1<1>.D 0.000 11.400 -11.400


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
AS to D<0> 0.000 26.600 -26.600
AS to D<10> 0.000 26.600 -26.600
AS to D<11> 0.000 26.600 -26.600


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
C1 to AUTO_CONFIG_DONE<0>.CLKF 0.000 13.900 -13.900
C1 to AUTO_CONFIG_DONE<1>.CLKF 0.000 13.900 -13.900
C1 to AUTO_CONFIG_DONE_CYCLE<0>.CLKF 0.000 13.900 -13.900


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CP_CS.Q to D<0> 0.000 20.400 -20.400
CP_CS.Q to D<10> 0.000 20.400 -20.400
CP_CS.Q to D<11> 0.000 20.400 -20.400



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
C1 71.429 Limited by Clock Pulse Width for C1
C3 71.429 Limited by Clock Pulse Width for C3
AS 71.429 Limited by Clock Pulse Width for AS

Setup/Hold Times for Clocks

Setup/Hold Times for Clock C1
Source Pad Setup to clk (edge) Hold to clk (edge)
A<1> -4.200 9.100
A<2> -4.200 9.100
A<3> -4.200 9.100
A<4> -4.200 9.100
A<5> -4.200 9.100
A<6> -4.200 9.100
AS -4.200 9.100
AUTOBOOT_OFF -4.200 7.700
D<10> -4.600 8.100
D<11> -4.600 8.100
D<12> -4.600 8.100
D<13> -4.600 8.100
D<14> -4.600 8.100
D<15> -4.600 8.100
D<8> -4.600 8.100
D<9> -4.600 8.100
LDS -4.200 9.100
RESET -4.200 9.100
RW -4.600 9.100
UDS -4.200 9.100

Setup/Hold Times for Clock C3
Source Pad Setup to clk (edge) Hold to clk (edge)
A<1> -4.200 9.100
A<2> -4.200 9.100
A<3> -4.200 9.100
A<4> -4.200 9.100
A<5> -4.200 9.100
A<6> -4.200 9.100
AS -4.200 9.100
AUTOBOOT_OFF -4.200 7.700
D<10> -4.600 8.100
D<11> -4.600 8.100
D<12> -4.600 8.100
D<13> -4.600 8.100
D<14> -4.600 8.100
D<15> -4.600 8.100
D<8> -4.600 8.100
D<9> -4.600 8.100
LDS -4.200 9.100
RESET -4.200 9.100
RW -4.600 9.100
UDS -4.200 9.100

Setup/Hold Times for Clock AS
Source Pad Setup to clk (edge) Hold to clk (edge)
A<16> 3.100 1.400
A<17> 3.100 1.400
A<18> 3.500 1.400
A<19> 3.100 1.400
A<20> 3.100 1.400
A<21> 3.100 1.400
A<22> 3.500 1.400
A<23> 3.500 1.400
CFIN 2.100 1.400


Clock to Pad Timing

Clock C1 to Pad
Destination Pad Clock (edge) to Pad
IDE_R 26.600
CFOUT 25.600
CP_RD 25.600
CP_WE 25.600
D<12> 25.600
D<13> 25.600
D<14> 25.600
D<15> 25.600
IDE_W 25.600
LAN_RD 25.600
LAN_WRH 25.600
LAN_WRL 25.600
ROM_OE 25.600

Clock C3 to Pad
Destination Pad Clock (edge) to Pad
IDE_R 26.600
CFOUT 25.600
CP_RD 25.600
CP_WE 25.600
D<12> 25.600
D<13> 25.600
D<14> 25.600
D<15> 25.600
IDE_W 25.600
LAN_RD 25.600
LAN_WRH 25.600
LAN_WRL 25.600
ROM_OE 25.600

Clock AS to Pad
Destination Pad Clock (edge) to Pad
D<0> 26.600
D<10> 26.600
D<11> 26.600
D<12> 26.600
D<13> 26.600
D<14> 26.600
D<15> 26.600
D<1> 26.600
D<2> 26.600
D<3> 26.600
D<4> 26.600
D<5> 26.600
D<6> 26.600
D<7> 26.600
D<8> 26.600
D<9> 26.600
DQ<0> 26.600
DQ<10> 26.600
DQ<11> 26.600
DQ<12> 26.600
DQ<13> 26.600
DQ<14> 26.600
DQ<15> 26.600
DQ<1> 26.600
DQ<2> 26.600
DQ<3> 26.600
DQ<4> 26.600
DQ<5> 26.600
DQ<6> 26.600
DQ<7> 26.600
DQ<8> 26.600
DQ<9> 26.600
OWN 26.600
DTACK 18.900
OVR 18.900
SLAVE 17.900
CP_CS 10.200
LAN_CS 10.200


Clock to Setup Times for Clocks

Clock to Setup for clock C1
Source Destination Delay
AUTO_CONFIG_DONE<0>.Q Dout1<0>.D 11.400
AUTO_CONFIG_DONE<1>.Q Dout1<0>.D 11.400
AUTO_CONFIG_DONE<1>.Q Dout1<1>.D 11.400
AUTO_CONFIG_DONE<1>.Q Dout1<2>.D 11.400
AUTO_CONFIG_DONE<0>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
AUTO_CONFIG_DONE<0>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<0>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<1>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<2>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<5>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<6>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE<0>.Q Dout1<2>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<0>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<1>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<2>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<5>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<6>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<0>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<1>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<2>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<5>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<6>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE<1>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
AUTO_CONFIG_DONE<1>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<0>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<1>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<2>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<5>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<6>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<0>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<1>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<2>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<5>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<6>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<0>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<1>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<2>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<5>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<6>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE_CYCLE<0>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
AUTO_CONFIG_DONE_CYCLE<0>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
AUTO_CONFIG_DONE_CYCLE<1>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
CP_BASEADR<0>.Q CP_BASEADR<0>.D 11.000
CP_BASEADR<1>.Q CP_BASEADR<1>.D 11.000
CP_BASEADR<2>.Q CP_BASEADR<2>.D 11.000
CP_BASEADR<3>.Q CP_BASEADR<3>.D 11.000
CP_BASEADR<4>.Q CP_BASEADR<4>.D 11.000
CP_BASEADR<5>.Q CP_BASEADR<5>.D 11.000
CP_BASEADR<6>.Q CP_BASEADR<6>.D 11.000
CP_BASEADR<7>.Q CP_BASEADR<7>.D 11.000
DS_D.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
DS_D.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
Dout1<0>.Q Dout1<0>.D 11.000
Dout1<1>.Q Dout1<1>.D 11.000
Dout1<3>.Q Dout1<3>.D 11.000
IDE_BASEADR<0>.Q IDE_BASEADR<0>.D 11.000
IDE_BASEADR<1>.Q IDE_BASEADR<1>.D 11.000
IDE_BASEADR<2>.Q IDE_BASEADR<2>.D 11.000
IDE_BASEADR<3>.Q IDE_BASEADR<3>.D 11.000
IDE_BASEADR<4>.Q IDE_BASEADR<4>.D 11.000
IDE_BASEADR<5>.Q IDE_BASEADR<5>.D 11.000
IDE_BASEADR<6>.Q IDE_BASEADR<6>.D 11.000
IDE_BASEADR<7>.Q IDE_BASEADR<7>.D 11.000
LAN_BASEADR<0>.Q LAN_BASEADR<0>.D 11.000
LAN_BASEADR<1>.Q LAN_BASEADR<1>.D 11.000
LAN_BASEADR<2>.Q LAN_BASEADR<2>.D 11.000
LAN_BASEADR<3>.Q LAN_BASEADR<3>.D 11.000
LAN_BASEADR<4>.Q LAN_BASEADR<4>.D 11.000
LAN_BASEADR<5>.Q LAN_BASEADR<5>.D 11.000
LAN_BASEADR<6>.Q LAN_BASEADR<6>.D 11.000
LAN_BASEADR<7>.Q LAN_BASEADR<7>.D 11.000
SHUT_UP<0>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<0>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<1>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<2>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<3>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<4>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<5>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<6>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<7>.D 11.000
SHUT_UP<1>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<0>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<1>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<2>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<3>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<4>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<5>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<6>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<7>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<0>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<1>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<2>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<3>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<4>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<5>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<6>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE<0>.Q AUTO_CONFIG_DONE<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q Dout1<1>.D 10.000
AUTO_CONFIG_DONE<0>.Q SHUT_UP<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q SHUT_UP<1>.D 10.000
AUTO_CONFIG_DONE<0>.Q SHUT_UP<2>.D 10.000
AUTO_CONFIG_DONE<1>.Q AUTO_CONFIG_DONE<1>.D 10.000
AUTO_CONFIG_DONE<1>.Q Dout1<3>.D 10.000
AUTO_CONFIG_DONE<1>.Q SHUT_UP<0>.D 10.000
AUTO_CONFIG_DONE<1>.Q SHUT_UP<1>.D 10.000
AUTO_CONFIG_DONE<1>.Q SHUT_UP<2>.D 10.000
AUTO_CONFIG_DONE_CYCLE<0>.Q AUTO_CONFIG_DONE<0>.D 10.000
AUTO_CONFIG_DONE_CYCLE<1>.Q AUTO_CONFIG_DONE<1>.D 10.000
Dout1<2>.Q Dout1<2>.D 10.000
IDE_ENABLE.Q IDE_ENABLE.D 10.000
IDE_ENABLE.Q IDE_R_S.D 10.000
IDE_ENABLE.Q ROM_OE_S.D 10.000
SHUT_UP<0>.Q SHUT_UP<0>.D 10.000
SHUT_UP<1>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 10.000
SHUT_UP<1>.Q SHUT_UP<1>.D 10.000
SHUT_UP<2>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 10.000
SHUT_UP<2>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 10.000
SHUT_UP<2>.Q SHUT_UP<2>.D 10.000

Clock to Setup for clock C3
Source Destination Delay
AUTO_CONFIG_DONE<0>.Q Dout1<0>.D 11.400
AUTO_CONFIG_DONE<1>.Q Dout1<0>.D 11.400
AUTO_CONFIG_DONE<1>.Q Dout1<1>.D 11.400
AUTO_CONFIG_DONE<1>.Q Dout1<2>.D 11.400
AUTO_CONFIG_DONE<0>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
AUTO_CONFIG_DONE<0>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<0>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<1>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<2>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<5>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<6>.D 11.000
AUTO_CONFIG_DONE<0>.Q CP_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE<0>.Q Dout1<2>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<0>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<1>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<2>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<5>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<6>.D 11.000
AUTO_CONFIG_DONE<0>.Q IDE_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<0>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<1>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<2>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<5>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<6>.D 11.000
AUTO_CONFIG_DONE<0>.Q LAN_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE<1>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
AUTO_CONFIG_DONE<1>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<0>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<1>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<2>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<5>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<6>.D 11.000
AUTO_CONFIG_DONE<1>.Q CP_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<0>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<1>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<2>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<5>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<6>.D 11.000
AUTO_CONFIG_DONE<1>.Q IDE_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<0>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<1>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<2>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<3>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<4>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<5>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<6>.D 11.000
AUTO_CONFIG_DONE<1>.Q LAN_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE_CYCLE<0>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
AUTO_CONFIG_DONE_CYCLE<0>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
AUTO_CONFIG_DONE_CYCLE<1>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
CP_BASEADR<0>.Q CP_BASEADR<0>.D 11.000
CP_BASEADR<1>.Q CP_BASEADR<1>.D 11.000
CP_BASEADR<2>.Q CP_BASEADR<2>.D 11.000
CP_BASEADR<3>.Q CP_BASEADR<3>.D 11.000
CP_BASEADR<4>.Q CP_BASEADR<4>.D 11.000
CP_BASEADR<5>.Q CP_BASEADR<5>.D 11.000
CP_BASEADR<6>.Q CP_BASEADR<6>.D 11.000
CP_BASEADR<7>.Q CP_BASEADR<7>.D 11.000
DS_D.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
DS_D.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
Dout1<0>.Q Dout1<0>.D 11.000
Dout1<1>.Q Dout1<1>.D 11.000
Dout1<3>.Q Dout1<3>.D 11.000
IDE_BASEADR<0>.Q IDE_BASEADR<0>.D 11.000
IDE_BASEADR<1>.Q IDE_BASEADR<1>.D 11.000
IDE_BASEADR<2>.Q IDE_BASEADR<2>.D 11.000
IDE_BASEADR<3>.Q IDE_BASEADR<3>.D 11.000
IDE_BASEADR<4>.Q IDE_BASEADR<4>.D 11.000
IDE_BASEADR<5>.Q IDE_BASEADR<5>.D 11.000
IDE_BASEADR<6>.Q IDE_BASEADR<6>.D 11.000
IDE_BASEADR<7>.Q IDE_BASEADR<7>.D 11.000
LAN_BASEADR<0>.Q LAN_BASEADR<0>.D 11.000
LAN_BASEADR<1>.Q LAN_BASEADR<1>.D 11.000
LAN_BASEADR<2>.Q LAN_BASEADR<2>.D 11.000
LAN_BASEADR<3>.Q LAN_BASEADR<3>.D 11.000
LAN_BASEADR<4>.Q LAN_BASEADR<4>.D 11.000
LAN_BASEADR<5>.Q LAN_BASEADR<5>.D 11.000
LAN_BASEADR<6>.Q LAN_BASEADR<6>.D 11.000
LAN_BASEADR<7>.Q LAN_BASEADR<7>.D 11.000
SHUT_UP<0>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<0>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<1>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<2>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<3>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<4>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<5>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<6>.D 11.000
SHUT_UP<0>.Q LAN_BASEADR<7>.D 11.000
SHUT_UP<1>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<0>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<1>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<2>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<3>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<4>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<5>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<6>.D 11.000
SHUT_UP<1>.Q CP_BASEADR<7>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<0>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<1>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<2>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<3>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<4>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<5>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<6>.D 11.000
SHUT_UP<2>.Q IDE_BASEADR<7>.D 11.000
AUTO_CONFIG_DONE<0>.Q AUTO_CONFIG_DONE<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q Dout1<1>.D 10.000
AUTO_CONFIG_DONE<0>.Q SHUT_UP<0>.D 10.000
AUTO_CONFIG_DONE<0>.Q SHUT_UP<1>.D 10.000
AUTO_CONFIG_DONE<0>.Q SHUT_UP<2>.D 10.000
AUTO_CONFIG_DONE<1>.Q AUTO_CONFIG_DONE<1>.D 10.000
AUTO_CONFIG_DONE<1>.Q Dout1<3>.D 10.000
AUTO_CONFIG_DONE<1>.Q SHUT_UP<0>.D 10.000
AUTO_CONFIG_DONE<1>.Q SHUT_UP<1>.D 10.000
AUTO_CONFIG_DONE<1>.Q SHUT_UP<2>.D 10.000
AUTO_CONFIG_DONE_CYCLE<0>.Q AUTO_CONFIG_DONE<0>.D 10.000
AUTO_CONFIG_DONE_CYCLE<1>.Q AUTO_CONFIG_DONE<1>.D 10.000
Dout1<2>.Q Dout1<2>.D 10.000
IDE_ENABLE.Q IDE_ENABLE.D 10.000
IDE_ENABLE.Q IDE_R_S.D 10.000
IDE_ENABLE.Q ROM_OE_S.D 10.000
SHUT_UP<0>.Q SHUT_UP<0>.D 10.000
SHUT_UP<1>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 10.000
SHUT_UP<1>.Q SHUT_UP<1>.D 10.000
SHUT_UP<2>.Q AUTO_CONFIG_DONE_CYCLE<0>.D 10.000
SHUT_UP<2>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 10.000
SHUT_UP<2>.Q SHUT_UP<2>.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
AS OWN 18.700
LDS D<0> 18.700
LDS D<10> 18.700
LDS D<11> 18.700
LDS D<12> 18.700
LDS D<13> 18.700
LDS D<14> 18.700
LDS D<15> 18.700
LDS D<1> 18.700
LDS D<2> 18.700
LDS D<3> 18.700
LDS D<4> 18.700
LDS D<5> 18.700
LDS D<6> 18.700
LDS D<7> 18.700
LDS D<8> 18.700
LDS D<9> 18.700
LDS DQ<0> 18.700
LDS DQ<10> 18.700
LDS DQ<11> 18.700
LDS DQ<12> 18.700
LDS DQ<13> 18.700
LDS DQ<14> 18.700
LDS DQ<15> 18.700
LDS DQ<1> 18.700
LDS DQ<2> 18.700
LDS DQ<3> 18.700
LDS DQ<4> 18.700
LDS DQ<5> 18.700
LDS DQ<6> 18.700
LDS DQ<7> 18.700
LDS DQ<8> 18.700
LDS DQ<9> 18.700
RW D<0> 18.700
RW D<10> 18.700
RW D<11> 18.700
RW D<12> 18.700
RW D<13> 18.700
RW D<14> 18.700
RW D<15> 18.700
RW D<1> 18.700
RW D<2> 18.700
RW D<3> 18.700
RW D<4> 18.700
RW D<5> 18.700
RW D<6> 18.700
RW D<7> 18.700
RW D<8> 18.700
RW D<9> 18.700
RW DQ<0> 18.700
RW DQ<10> 18.700
RW DQ<11> 18.700
RW DQ<12> 18.700
RW DQ<13> 18.700
RW DQ<14> 18.700
RW DQ<15> 18.700
RW DQ<1> 18.700
RW DQ<2> 18.700
RW DQ<3> 18.700
RW DQ<4> 18.700
RW DQ<5> 18.700
RW DQ<6> 18.700
RW DQ<7> 18.700
RW DQ<8> 18.700
RW DQ<9> 18.700
UDS D<0> 18.700
UDS D<10> 18.700
UDS D<11> 18.700
UDS D<12> 18.700
UDS D<13> 18.700
UDS D<14> 18.700
UDS D<15> 18.700
UDS D<1> 18.700
UDS D<2> 18.700
UDS D<3> 18.700
UDS D<4> 18.700
UDS D<5> 18.700
UDS D<6> 18.700
UDS D<7> 18.700
UDS D<8> 18.700
UDS D<9> 18.700
UDS DQ<0> 18.700
UDS DQ<10> 18.700
UDS DQ<11> 18.700
UDS DQ<12> 18.700
UDS DQ<13> 18.700
UDS DQ<14> 18.700
UDS DQ<15> 18.700
UDS DQ<1> 18.700
UDS DQ<2> 18.700
UDS DQ<3> 18.700
UDS DQ<4> 18.700
UDS DQ<5> 18.700
UDS DQ<6> 18.700
UDS DQ<7> 18.700
UDS DQ<8> 18.700
UDS DQ<9> 18.700
A<6> A_LAN<5> 11.000
AS DTACK 11.000
AS IDE_R 11.000
AS OVR 11.000
DQ<12> D<12> 11.000
DQ<13> D<13> 11.000
DQ<14> D<14> 11.000
DQ<15> D<15> 11.000
IDE_WAIT DTACK 11.000
A<10> A_LAN<9> 10.000
A<10> IDE_A<1> 10.000
A<11> A_LAN<10> 10.000
A<11> IDE_A<2> 10.000
A<12> A_LAN<11> 10.000
A<12> IDE_CS<0> 10.000
A<13> A_LAN<12> 10.000
A<13> IDE_CS<1> 10.000
A<14> A_LAN<13> 10.000
A<1> A_LAN<0> 10.000
A<2> A_LAN<1> 10.000
A<3> A_LAN<2> 10.000
A<4> A_LAN<3> 10.000
A<5> A_LAN<4> 10.000
A<7> A_LAN<6> 10.000
A<8> A_LAN<7> 10.000
A<9> A_LAN<8> 10.000
A<9> IDE_A<0> 10.000
AS CP_RD 10.000
AS CP_WE 10.000
AS IDE_W 10.000
AS LAN_RD 10.000
AS LAN_WRH 10.000
AS LAN_WRL 10.000
AS ROM_OE 10.000
AS SLAVE 10.000
D<0> DQ<0> 10.000
D<1> DQ<1> 10.000
D<2> DQ<2> 10.000
D<3> DQ<3> 10.000
D<4> DQ<4> 10.000
D<5> DQ<5> 10.000
D<6> DQ<6> 10.000
D<7> DQ<7> 10.000
DQ<0> D<0> 10.000
DQ<10> D<10> 10.000
DQ<11> D<11> 10.000
DQ<1> D<1> 10.000
DQ<2> D<2> 10.000
DQ<3> D<3> 10.000
DQ<4> D<4> 10.000
DQ<5> D<5> 10.000
DQ<6> D<6> 10.000
DQ<7> D<7> 10.000
DQ<8> D<8> 10.000
DQ<9> D<9> 10.000
D<10> DQ<10> 6.500
D<11> DQ<11> 6.500
D<12> DQ<12> 6.500
D<13> DQ<13> 6.500
D<14> DQ<14> 6.500
D<15> DQ<15> 6.500
D<8> DQ<8> 6.500
D<9> DQ<9> 6.500


Number of paths analyzed: 1082
Number of Timing errors: 1082
Analysis Completed: Sat Jan 14 23:47:44 2017