| [Warning]:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'LAN_IDE_CP.ise'.INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC constraint 'P30'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. |
| [Warning]:Cpld:1007 - Removing unused input(s) 'DS0'. The input(s) are unused after optimization. Please verify functionality via simulation. |
| [Warning]:Cpld:1007 - Removing unused input(s) 'DS1'. The input(s) are unused after optimization. Please verify functionality via simulation. |
| [Warning]:Cpld:1007 - Removing unused input(s) 'FCS'. The input(s) are unused after optimization. Please verify functionality via simulation. |
| [Warning]:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused after optimization. Please verify functionality via simulation. |
| [Warning]:Cpld:1007 - Removing unused input(s) 'Z3'. The input(s) are unused after optimization. Please verify functionality via simulation. |
| [Warning]:Cpld:896 - Unable to map all desired signals into function block, FB10, because too many function block product terms are required. Buffering output signal DQ<8> to allow all signals assigned to this function block to be placed. |
| [Warning]:Cpld:896 - Unable to map all desired signals into function block, FB10, because too many function block product terms are required. Buffering output signal DQ<4> to allow all signals assigned to this function block to be placed. |
| [Warning]:Cpld:896 - Unable to map all desired signals into function block, FB10, because too many function block product terms are required. Buffering output signal DQ<10> to allow all signals assigned to this function block to be placed. |
| [Warning]:Cpld:896 - Unable to map all desired signals into function block, FB10, because too many function block product terms are required. Buffering output signal DQ<7> to allow all signals assigned to this function block to be placed. |
| [Warning]:Cpld:896 - Unable to map all desired signals into function block, FB10, because too many function block product terms are required. Buffering output signal DQ<6> to allow all signals assigned to this function block to be placed. |
| [Warning]:Cpld:896 - Unable to map all desired signals into function block, FB10, because too many function block product terms are required. Buffering output signal DQ<5> to allow all signals assigned to this function block to be placed. |
| [Warning]:Cpld:896 - Unable to map all desired signals into function block, FB10, because too many function block product terms are required. Buffering output signal DQ<3> to allow all signals assigned to this function block to be placed. |
| [Warning]:Cpld:896 - Unable to map all desired signals into function block, FB12, because too many function block product terms are required. Buffering output signal DQ<9> to allow all signals assigned to this function block to be placed. |