| Design Name | LAN_IDE_CP |
| Fitting Status | Successful |
| Software Version | P.68d |
| Device Used | XC95288XL-10-TQ144 |
| Date | 1-27-2017, 11:27PM |
| Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
|---|---|---|---|---|
| 137/288 (48%) | 653/1440 (46%) | 56/288 (20%) | 111/117 (95%) | 402/864 (47%) |
|
|
| Signal mapped onto global clock net (GCK1) | CLK_EXT |
| Signal mapped onto global output enable net (GSR) | RESET |
| Macrocells in high performance mode (MCHP) | 137 |
| Macrocells in low power mode (MCLP) | 0 |
| Total macrocells used (MC) | 137 |