Equations

********** Mapped Logic **********
$OpTx$FX_DC$14 <= (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5 AND
      NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
      NOT LAN_SM_FSM_FFd9 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd11 AND
      NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd4);
$OpTx$FX_DC$18 <= (DS1 AND DS0);
$OpTx$FX_DC$19 <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
$OpTx$FX_DC$22 <= (RESET AND NOT FCS);
$OpTx$FX_DC$25 <= (NOT RW AND lan_adr AND Z3_ADR(13) AND NOT Z3_DS/Z3_DS_D2);
$OpTx$FX_DC$4 <= (UDS AND LDS);
$OpTx$FX_DC$7 <= ((LAN_SM_FSM_FFd3)
      OR (LAN_SM_FSM_FFd12 AND $OpTx$FX_DC$4));
$OpTx$FX_SC$29 <= (LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
      NOT Z3_DS/Z3_DS_D2);
FDCPE_A8: FDCPE port map (A_I(8),DQ(0).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(8) <= A_I(8) when A_OE(8) = '1' else 'Z';
     A_OE(8) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A9: FDCPE port map (A_I(9),DQ(1).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(9) <= A_I(9) when A_OE(9) = '1' else 'Z';
     A_OE(9) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A10: FDCPE port map (A_I(10),DQ(2).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(10) <= A_I(10) when A_OE(10) = '1' else 'Z';
     A_OE(10) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A11: FDCPE port map (A_I(11),DQ(3).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(11) <= A_I(11) when A_OE(11) = '1' else 'Z';
     A_OE(11) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A12: FDCPE port map (A_I(12),DQ(4).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(12) <= A_I(12) when A_OE(12) = '1' else 'Z';
     A_OE(12) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A13: FDCPE port map (A_I(13),DQ(5).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(13) <= A_I(13) when A_OE(13) = '1' else 'Z';
     A_OE(13) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A14: FDCPE port map (A_I(14),DQ(6).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(14) <= A_I(14) when A_OE(14) = '1' else 'Z';
     A_OE(14) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A15: FDCPE port map (A_I(15),DQ(7).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(15) <= A_I(15) when A_OE(15) = '1' else 'Z';
     A_OE(15) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A16: FDCPE port map (A_I(16),DQ(8).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(16) <= A_I(16) when A_OE(16) = '1' else 'Z';
     A_OE(16) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A17: FDCPE port map (A_I(17),DQ(9).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(17) <= A_I(17) when A_OE(17) = '1' else 'Z';
     A_OE(17) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A18: FDCPE port map (A_I(18),DQ(10).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(18) <= A_I(18) when A_OE(18) = '1' else 'Z';
     A_OE(18) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A19: FDCPE port map (A_I(19),DQ(11).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(19) <= A_I(19) when A_OE(19) = '1' else 'Z';
     A_OE(19) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A20: FDCPE port map (A_I(20),DQ(12).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(20) <= A_I(20) when A_OE(20) = '1' else 'Z';
     A_OE(20) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A21: FDCPE port map (A_I(21),DQ(13).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(21) <= A_I(21) when A_OE(21) = '1' else 'Z';
     A_OE(21) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A22: FDCPE port map (A_I(22),DQ(14).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(22) <= A_I(22) when A_OE(22) = '1' else 'Z';
     A_OE(22) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FDCPE_A23: FDCPE port map (A_I(23),DQ(15).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5);
     A(23) <= A_I(23) when A_OE(23) = '1' else 'Z';
     A_OE(23) <= (RW AND NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2);
FTCPE_AUTO_CONFIG_DONE_CYCLE: FTCPE port map (AUTO_CONFIG_DONE_CYCLE,AUTO_CONFIG_DONE_CYCLE_T,CLK_EXT,NOT RESET,'0');
     AUTO_CONFIG_DONE_CYCLE_T <= (NOT AUTO_CONFIG_DONE_CYCLE AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND
      Z3_ADR_1 AND NOT Z3_ADR(6) AND autoconfig AND NOT Z3_ADR(3) AND Z3_ADR(4) AND
      NOT Z3_ADR(5) AND NOT Z3_DS/Z3_DS_D2);
A_LAN(0) <= NOT ((RESET AND NOT Z3_A_LOW));
A_LAN(1) <= NOT ((RESET AND NOT Z3_ADR_0));
A_LAN(2) <= NOT ((RESET AND NOT Z3_ADR_1));
A_LAN(3) <= ((RESET AND Z3_ADR(2))
      OR (NOT RESET AND LAN_A_INIT(3)));
A_LAN(4) <= NOT ((RESET AND NOT Z3_ADR(3)));
A_LAN(5) <= NOT ((RESET AND NOT Z3_ADR(4)));
A_LAN(6) <= ((RESET AND Z3_ADR(5))
      OR (NOT RESET AND LAN_A_INIT(6)));
A_LAN(7) <= NOT ((RESET AND NOT Z3_ADR(6)));
A_LAN(8) <= NOT ((RESET AND NOT Z3_ADR(7)));
A_LAN(9) <= NOT ((RESET AND NOT Z3_ADR(8)));
A_LAN(10) <= NOT ((RESET AND NOT Z3_ADR(9)));
A_LAN(11) <= NOT ((RESET AND NOT Z3_ADR(10)));
A_LAN(12) <= NOT ((RESET AND NOT Z3_ADR(11)));
A_LAN(13) <= NOT ((RESET AND NOT Z3_ADR(12)));
BUF_LAN_SM_FSM_FFd9 <= (NOT RW AND LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
      NOT $OpTx$FX_DC$4);
FDCPE_CFOUT: FDCPE port map (CFOUT,CFOUT_D,CLK_EXT,'0',NOT RESET,FCS);
     CFOUT_D <= (NOT AUTO_CONFIG_DONE_CYCLE AND AUTOBOOT_OFF);
CP_CS <= '1';
CP_RD <= '1';
CP_WE <= '1';
D_I(0) <= NOT ((NOT Z3_DATA(16) AND $OpTx$FX_DC$19));
     D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
     D_OE(0) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(1) <= NOT ((NOT Z3_DATA(17) AND $OpTx$FX_DC$19));
     D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
     D_OE(1) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(2) <= NOT ((NOT Z3_DATA(18) AND $OpTx$FX_DC$19));
     D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
     D_OE(2) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(3) <= NOT ((NOT Z3_DATA(19) AND $OpTx$FX_DC$19));
     D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
     D_OE(3) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(4) <= NOT ((NOT Z3_DATA(20) AND $OpTx$FX_DC$19));
     D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
     D_OE(4) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(5) <= NOT ((NOT Z3_DATA(21) AND $OpTx$FX_DC$19));
     D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
     D_OE(5) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(6) <= NOT ((NOT Z3_DATA(22) AND $OpTx$FX_DC$19));
     D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
     D_OE(6) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(7) <= NOT ((NOT Z3_DATA(23) AND $OpTx$FX_DC$19));
     D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
     D_OE(7) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(8) <= ((Z3_DATA(24) AND $OpTx$FX_DC$19)
      OR (Dout1(0) AND NOT $OpTx$FX_DC$19));
     D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
     D_OE(8) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(9) <= ((Z3_DATA(25) AND $OpTx$FX_DC$19)
      OR (Dout1(1) AND NOT $OpTx$FX_DC$19));
     D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
     D_OE(9) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(10) <= ((Z3_DATA(26) AND $OpTx$FX_DC$19)
      OR (Dout1(2) AND NOT $OpTx$FX_DC$19));
     D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
     D_OE(10) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(11) <= ((Z3_DATA(27) AND $OpTx$FX_DC$19)
      OR (Dout1(3) AND NOT $OpTx$FX_DC$19));
     D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
     D_OE(11) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(12) <= ((Z3_DATA(28) AND $OpTx$FX_DC$19)
      OR (Dout1(4) AND NOT $OpTx$FX_DC$19));
     D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
     D_OE(12) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(13) <= ((Z3_DATA(29) AND $OpTx$FX_DC$19)
      OR (Dout1(5) AND NOT $OpTx$FX_DC$19));
     D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
     D_OE(13) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(14) <= ((Z3_DATA(30) AND $OpTx$FX_DC$19)
      OR (Dout1(6) AND NOT $OpTx$FX_DC$19));
     D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
     D_OE(14) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
D_I(15) <= ((Z3_DATA(31) AND $OpTx$FX_DC$19)
      OR (Dout1(7) AND NOT $OpTx$FX_DC$19));
     D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
     D_OE(15) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
DQ_I(0) <= (RESET AND DQ_DATA(0));
     DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z';
     DQ_OE(0) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(1) <= ((RESET AND DQ_DATA(1))
      OR (NOT RESET AND LAN_D_INIT(1)));
     DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z';
     DQ_OE(1) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(2) <= (RESET AND DQ_DATA(2));
     DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z';
     DQ_OE(2) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(3) <= (RESET AND DQ_DATA(3));
     DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z';
     DQ_OE(3) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(4) <= ((RESET AND DQ_DATA(4))
      OR (NOT RESET AND LAN_D_INIT(1)));
     DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z';
     DQ_OE(4) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(5) <= (RESET AND DQ_DATA(5));
     DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z';
     DQ_OE(5) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(6) <= (RESET AND DQ_DATA(6));
     DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z';
     DQ_OE(6) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(7) <= (RESET AND DQ_DATA(7));
     DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z';
     DQ_OE(7) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(8) <= ((RESET AND DQ_DATA(8))
      OR (NOT RESET AND LAN_D_INIT(8)));
     DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z';
     DQ_OE(8) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(9) <= ((RESET AND DQ_DATA(9))
      OR (NOT RESET AND LAN_D_INIT(1)));
     DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z';
     DQ_OE(9) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(10) <= ((RESET AND DQ_DATA(10))
      OR (NOT RESET AND LAN_D_INIT(8)));
     DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z';
     DQ_OE(10) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(11) <= ((RESET AND DQ_DATA(11))
      OR (NOT RESET AND LAN_D_INIT(8)));
     DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z';
     DQ_OE(11) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(12) <= (RESET AND DQ_DATA(12));
     DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z';
     DQ_OE(12) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(13) <= (RESET AND DQ_DATA(13));
     DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z';
     DQ_OE(13) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(14) <= (RESET AND DQ_DATA(14));
     DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z';
     DQ_OE(14) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(15) <= (RESET AND DQ_DATA(15));
     DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z';
     DQ_OE(15) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST <= ((NOT RESET)
      OR (NOT FCS AND lan_adr AND NOT Z3_DS/Z3_DS_D2 AND NOT $OpTx$FX_DC$19));
FDCPE_DQ_DATA0: FDCPE port map (DQ_DATA(0),DQ_DATA_D(0),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(0) <= ((A(8).PIN AND $OpTx$FX_DC$7)
      OR (DQ_DATA(0) AND NOT $OpTx$FX_DC$14)
      OR (LAN_SM_FSM_FFd12 AND D(0).PIN AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA1: FDCPE port map (DQ_DATA(1),DQ_DATA_D(1),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(1) <= ((DQ_DATA(1) AND NOT $OpTx$FX_DC$14)
      OR (A(9).PIN AND $OpTx$FX_DC$7)
      OR (LAN_SM_FSM_FFd12 AND D(1).PIN AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA2: FDCPE port map (DQ_DATA(2),DQ_DATA_D(2),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(2) <= ((DQ_DATA(2) AND NOT $OpTx$FX_DC$14)
      OR (A(10).PIN AND $OpTx$FX_DC$7)
      OR (LAN_SM_FSM_FFd12 AND D(2).PIN AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA3: FDCPE port map (DQ_DATA(3),DQ_DATA_D(3),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(3) <= ((DQ_DATA(3) AND NOT $OpTx$FX_DC$14)
      OR (A(11).PIN AND $OpTx$FX_DC$7)
      OR (LAN_SM_FSM_FFd12 AND D(3).PIN AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA4: FDCPE port map (DQ_DATA(4),DQ_DATA_D(4),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(4) <= ((DQ_DATA(4) AND NOT $OpTx$FX_DC$14)
      OR (A(12).PIN AND $OpTx$FX_DC$7)
      OR (LAN_SM_FSM_FFd12 AND D(4).PIN AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA5: FDCPE port map (DQ_DATA(5),DQ_DATA_D(5),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(5) <= ((DQ_DATA(5) AND NOT $OpTx$FX_DC$14)
      OR (A(13).PIN AND $OpTx$FX_DC$7)
      OR (LAN_SM_FSM_FFd12 AND D(5).PIN AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA6: FDCPE port map (DQ_DATA(6),DQ_DATA_D(6),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(6) <= ((DQ_DATA(6) AND NOT $OpTx$FX_DC$14)
      OR (A(14).PIN AND $OpTx$FX_DC$7)
      OR (LAN_SM_FSM_FFd12 AND D(6).PIN AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA7: FDCPE port map (DQ_DATA(7),DQ_DATA_D(7),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(7) <= ((A(15).PIN AND $OpTx$FX_DC$7)
      OR (DQ_DATA(7) AND NOT $OpTx$FX_DC$14)
      OR (LAN_SM_FSM_FFd12 AND D(7).PIN AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA8: FDCPE port map (DQ_DATA(8),DQ_DATA_D(8),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(8) <= ((A(16).PIN AND $OpTx$FX_DC$7)
      OR (DQ_DATA(8) AND NOT $OpTx$FX_DC$14)
      OR (D(8).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA9: FDCPE port map (DQ_DATA(9),DQ_DATA_D(9),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(9) <= ((A(17).PIN AND $OpTx$FX_DC$7)
      OR (DQ_DATA(9) AND NOT $OpTx$FX_DC$14)
      OR (D(9).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA10: FDCPE port map (DQ_DATA(10),DQ_DATA_D(10),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(10) <= ((A(18).PIN AND $OpTx$FX_DC$7)
      OR (DQ_DATA(10) AND NOT $OpTx$FX_DC$14)
      OR (D(10).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA11: FDCPE port map (DQ_DATA(11),DQ_DATA_D(11),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(11) <= ((A(19).PIN AND $OpTx$FX_DC$7)
      OR (DQ_DATA(11) AND NOT $OpTx$FX_DC$14)
      OR (D(11).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA12: FDCPE port map (DQ_DATA(12),DQ_DATA_D(12),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(12) <= ((A(20).PIN AND $OpTx$FX_DC$7)
      OR (DQ_DATA(12) AND NOT $OpTx$FX_DC$14)
      OR (D(12).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA13: FDCPE port map (DQ_DATA(13),DQ_DATA_D(13),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(13) <= ((A(21).PIN AND $OpTx$FX_DC$7)
      OR (DQ_DATA(13) AND NOT $OpTx$FX_DC$14)
      OR (D(13).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA14: FDCPE port map (DQ_DATA(14),DQ_DATA_D(14),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(14) <= ((A(22).PIN AND $OpTx$FX_DC$7)
      OR (DQ_DATA(14) AND NOT $OpTx$FX_DC$14)
      OR (D(14).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
FDCPE_DQ_DATA15: FDCPE port map (DQ_DATA(15),DQ_DATA_D(15),CLK_EXT,'0',LAN_SM_RST);
     DQ_DATA_D(15) <= ((A(23).PIN AND $OpTx$FX_DC$7)
      OR (DQ_DATA(15) AND NOT $OpTx$FX_DC$14)
      OR (D(15).PIN AND LAN_SM_FSM_FFd12 AND NOT $OpTx$FX_DC$4));
DTACK_I <= '0';
     DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
     DTACK_OE <= N0$BUF7/N0$BUF7_TRST;
D_9_IOBUFE/D_9_IOBUFE_TRST <= (($OpTx$FX_DC$19)
      OR (RW AND NOT FCS AND autoconfig AND NOT Z3_DS/Z3_DS_D2));
FDCPE_Dout10: FDCPE port map (Dout1(0),Dout1_D(0),CLK_EXT,'0',NOT RESET);
     Dout1_D(0) <= (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
      autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
      NOT Z3_DS/Z3_DS_D2);
FDCPE_Dout11: FDCPE port map (Dout1(1),Dout1_D(1),CLK_EXT,'0',NOT RESET);
     Dout1_D(1) <= ((NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND autoconfig AND
      NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT Z3_DS/Z3_DS_D2)
      OR (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND autoconfig AND
      NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT Z3_DS/Z3_DS_D2)
      OR (NOT FCS AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND autoconfig AND
      NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT Z3_DS/Z3_DS_D2));
FDCPE_Dout12: FDCPE port map (Dout1(2),Dout1_D(2),CLK_EXT,'0',NOT RESET);
     Dout1_D(2) <= ((NOT FCS AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
      autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
      NOT Z3_DS/Z3_DS_D2)
      OR (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
      autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
      NOT Z3_DS/Z3_DS_D2));
FDCPE_Dout13: FDCPE port map (Dout1(3),Dout1_D(3),CLK_EXT,'0',NOT RESET);
     Dout1_D(3) <= (NOT FCS AND NOT Z3_ADR_1 AND autoconfig AND NOT Z3_ADR(3) AND
      NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT Z3_DS/Z3_DS_D2);
FDCPE_Dout14: FDCPE port map (Dout1(4),Dout1_D(4),CLK_EXT,'0',NOT RESET);
     Dout1_D(4) <= ((NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
      autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
      NOT Z3_DS/Z3_DS_D2)
      OR (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND NOT Z3_ADR(6) AND
      autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
      NOT Z3_DS/Z3_DS_D2)
      OR (NOT FCS AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
      autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
      NOT Z3_DS/Z3_DS_D2));
FDCPE_Dout15: FDCPE port map (Dout1(5),Dout1_D(5),CLK_EXT,'0',NOT RESET);
     Dout1_D(5) <= ((NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND autoconfig AND
      NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT Z3_DS/Z3_DS_D2)
      OR (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND Z3_ADR(6) AND
      autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
      NOT Z3_DS/Z3_DS_D2)
      OR (NOT FCS AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND Z3_ADR(6) AND
      autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
      NOT Z3_DS/Z3_DS_D2));
FDCPE_Dout16: FDCPE port map (Dout1(6),Dout1_D(6),CLK_EXT,'0',NOT RESET);
     Dout1_D(6) <= ((NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
      autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
      NOT Z3_DS/Z3_DS_D2)
      OR (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR(6) AND
      autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
      NOT Z3_DS/Z3_DS_D2)
      OR (NOT FCS AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
      Z3_ADR(6) AND autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
      NOT Z3_DS/Z3_DS_D2));
FDCPE_Dout17: FDCPE port map (Dout1(7),Dout1_D(7),CLK_EXT,'0',NOT RESET);
     Dout1_D(7) <= (NOT FCS AND NOT Z3_ADR_1 AND Z3_ADR(6) AND autoconfig AND
      NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT Z3_DS/Z3_DS_D2);
IDE_A(0) <= '1';
IDE_A(1) <= '1';
IDE_A(2) <= '1';
IDE_CS(0) <= '1';
IDE_CS(1) <= '1';
IDE_R <= '1';
IDE_W <= '1';
INT_OUT_I <= '0';
     INT_OUT <= INT_OUT_I when INT_OUT_OE = '1' else 'Z';
     INT_OUT_OE <= (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT);
FDCPE_LAN_A_INIT3: FDCPE port map (LAN_A_INIT(3),'0',CLK_EXT,'0',RESET);
FDCPE_LAN_A_INIT6: FDCPE port map (LAN_A_INIT(6),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,'0',RESET);
LAN_CFG_I(1) <= '0';
     LAN_CFG(1) <= LAN_CFG_I(1) when LAN_CFG_OE(1) = '1' else 'Z';
     LAN_CFG_OE(1) <= '0';
LAN_CFG_I(2) <= '0';
     LAN_CFG(2) <= LAN_CFG_I(2) when LAN_CFG_OE(2) = '1' else 'Z';
     LAN_CFG_OE(2) <= '0';
LAN_CFG_I(3) <= '0';
     LAN_CFG(3) <= LAN_CFG_I(3) when LAN_CFG_OE(3) = '1' else 'Z';
     LAN_CFG_OE(3) <= '0';
LAN_CFG_I(4) <= '0';
     LAN_CFG(4) <= LAN_CFG_I(4) when LAN_CFG_OE(4) = '1' else 'Z';
     LAN_CFG_OE(4) <= '0';
LAN_CS <= ((RESET AND lan_adr)
      OR (NOT RESET AND LAN_CS_RST));
FDCPE_LAN_CS_RST: FDCPE port map (LAN_CS_RST,LAN_CS_RST_D,CLK_EXT,RESET,'0');
     LAN_CS_RST_D <= (NOT LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd3);
FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0');
FDCPE_LAN_D_INIT8: FDCPE port map (LAN_D_INIT(8),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0');
FDCPE_LAN_INT_ENABLE: FDCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_D,CLK_EXT,NOT RESET,'0');
     LAN_INT_ENABLE_D <= ((D(15).PIN AND $OpTx$FX_DC$25)
      OR (LAN_INT_ENABLE AND NOT $OpTx$FX_DC$25));
FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,CLK_EXT,'0',NOT RESET);
FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,CLK_EXT,'0',NOT RESET);
     LAN_IRQ_OUT_D <= ((NOT LAN_INT AND LAN_IRQ_D0)
      OR (NOT D(14).PIN AND LAN_INT_ENABLE AND NOT LAN_INT AND
      $OpTx$FX_DC$25)
      OR (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT AND NOT LAN_INT AND
      NOT $OpTx$FX_DC$25));
LAN_RD <= (LAN_RD_S AND $OpTx$FX_DC$22);
FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,CLK_EXT,LAN_SM_RST,'0');
     LAN_RD_S_D <= ((NOT RW AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
      NOT LAN_SM_FSM_FFd11)
      OR (NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
      NOT LAN_SM_FSM_FFd11 AND NOT $OpTx$FX_SC$29));
FTCPE_LAN_RST_SM_FSM_FFd1: FTCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_T,CLK_EXT,RESET,'0');
     LAN_RST_SM_FSM_FFd1_T <= (NOT LAN_RST_SM_FSM_FFd1 AND LAN_RST_SM_FSM_FFd2 AND
      NOT LAN_RST_SM_FSM_FFd3);
FDCPE_LAN_RST_SM_FSM_FFd2: FDCPE port map (LAN_RST_SM_FSM_FFd2,LAN_RST_SM_FSM_FFd2_D,CLK_EXT,RESET,'0');
     LAN_RST_SM_FSM_FFd2_D <= ((NOT LAN_RST_SM_FSM_FFd1 AND LAN_RST_SM_FSM_FFd3)
      OR (LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd3));
FDCPE_LAN_RST_SM_FSM_FFd3: FDCPE port map (LAN_RST_SM_FSM_FFd3,LAN_RST_SM_FSM_FFd3_D,CLK_EXT,RESET,'0');
     LAN_RST_SM_FSM_FFd3_D <= LAN_RST_SM_FSM_FFd1
      XOR
     LAN_RST_SM_FSM_FFd3_D <= LAN_RST_SM_FSM_FFd2;
FDCPE_LAN_SM_FSM_FFd1: FDCPE port map (LAN_SM_FSM_FFd1,LAN_SM_FSM_FFd1_D,CLK_EXT,LAN_SM_RST,'0');
     LAN_SM_FSM_FFd1_D <= (NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd2);
FDCPE_LAN_SM_FSM_FFd10: FDCPE port map (LAN_SM_FSM_FFd10,LAN_SM_FSM_FFd10_D,CLK_EXT,LAN_SM_RST,'0');
     LAN_SM_FSM_FFd10_D <= ((LAN_SM_FSM_FFd6)
      OR (RW AND LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
      NOT Z3_DS/Z3_DS_D2 AND $OpTx$FX_DC$4));
FDCPE_LAN_SM_FSM_FFd11: FDCPE port map (LAN_SM_FSM_FFd11,LAN_SM_FSM_FFd11_D,CLK_EXT,LAN_SM_RST,'0');
     LAN_SM_FSM_FFd11_D <= (RW AND LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
      NOT $OpTx$FX_DC$4);
FTCPE_LAN_SM_FSM_FFd12: FTCPE port map (LAN_SM_FSM_FFd12,LAN_SM_FSM_FFd12_T,CLK_EXT,'0',LAN_SM_RST);
     LAN_SM_FSM_FFd12_T <= (LAN_SM_FSM_FFd12 AND lan_adr AND NOT Z3_ADR(13) AND
      NOT Z3_DS/Z3_DS_D2);
FDCPE_LAN_SM_FSM_FFd2: FDCPE port map (LAN_SM_FSM_FFd2,LAN_SM_FSM_FFd8,CLK_EXT,LAN_SM_RST,'0');
FDCPE_LAN_SM_FSM_FFd3: FDCPE port map (LAN_SM_FSM_FFd3,LAN_SM_FSM_FFd3_D,CLK_EXT,LAN_SM_RST,'0');
     LAN_SM_FSM_FFd3_D <= ((LAN_SM_FSM_FFd4)
      OR (LAN_SM_FSM_FFd3 AND $OpTx$FX_DC$18));
FDCPE_LAN_SM_FSM_FFd4: FDCPE port map (LAN_SM_FSM_FFd4,LAN_SM_FSM_FFd9,CLK_EXT,LAN_SM_RST,'0');
FDCPE_LAN_SM_FSM_FFd5: FDCPE port map (LAN_SM_FSM_FFd5,LAN_SM_FSM_FFd5_D,CLK_EXT,LAN_SM_RST,'0');
     LAN_SM_FSM_FFd5_D <= (NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd10);
FDCPE_LAN_SM_FSM_FFd6: FDCPE port map (LAN_SM_FSM_FFd6,LAN_SM_FSM_FFd6_D,CLK_EXT,LAN_SM_RST,'0');
     LAN_SM_FSM_FFd6_D <= (LAN_SM_FSM_FFd7 AND NOT $OpTx$FX_DC$18);
FDCPE_LAN_SM_FSM_FFd7: FDCPE port map (LAN_SM_FSM_FFd7,LAN_SM_FSM_FFd7_D,CLK_EXT,LAN_SM_RST,'0');
     LAN_SM_FSM_FFd7_D <= ((LAN_SM_FSM_FFd11)
      OR (LAN_SM_FSM_FFd7 AND $OpTx$FX_DC$18));
FDCPE_LAN_SM_FSM_FFd8: FDCPE port map (LAN_SM_FSM_FFd8,LAN_SM_FSM_FFd8_D,CLK_EXT,LAN_SM_RST,'0');
     LAN_SM_FSM_FFd8_D <= ((LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$18)
      OR (NOT RW AND NOT BUF_LAN_SM_FSM_FFd9 AND $OpTx$FX_SC$29));
FDCPE_LAN_SM_FSM_FFd9: FDCPE port map (LAN_SM_FSM_FFd9,BUF_LAN_SM_FSM_FFd9,CLK_EXT,LAN_SM_RST,'0');
FDCPE_LAN_SM_RST: FDCPE port map (LAN_SM_RST,LAN_SM_RST_D,CLK_EXT,'0','0');
     LAN_SM_RST_D <= (RESET AND NOT FCS AND NOT Z3_DS/Z3_DS_D2);
LAN_WRH <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$22)
      OR (LAN_WRH_S AND $OpTx$FX_DC$22));
FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,CLK_EXT,LAN_SM_RST,'0');
     LAN_WRH_S_D <= ((NOT LDS AND LAN_SM_FSM_FFd9)
      OR (NOT DS0 AND LAN_SM_FSM_FFd8));
LAN_WRL <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$22)
      OR (LAN_WRL_S AND $OpTx$FX_DC$22));
FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,CLK_EXT,LAN_SM_RST,'0');
     LAN_WRL_S_D <= ((NOT UDS AND LAN_SM_FSM_FFd9)
      OR (NOT DS1 AND LAN_SM_FSM_FFd8));
FDCPE_LAN_WR_RST: FDCPE port map (LAN_WR_RST,LAN_WR_RST_D,CLK_EXT,RESET,'0');
     LAN_WR_RST_D <= (LAN_RST_SM_FSM_FFd2 AND LAN_RST_SM_FSM_FFd3);
MTACK_I <= '0';
     MTACK <= MTACK_I when MTACK_OE = '1' else 'Z';
     MTACK_OE <= '0';
N0$BUF7/N0$BUF7_TRST <= ((NOT FCS AND autoconfig)
      OR (NOT FCS AND lan_rdy));
OVR_I <= '0';
     OVR <= OVR_I when OVR_OE = '1' else 'Z';
     OVR_OE <= '0';
OWN_I <= '0';
     OWN <= OWN_I when OWN_OE = '1' else 'Z';
     OWN_OE <= '0';
ROM_B(0) <= '1';
ROM_B(1) <= '1';
ROM_OE <= '1';
FTCPE_SHUT_UP: FTCPE port map (SHUT_UP,SHUT_UP_T,CLK_EXT,'0',NOT RESET);
     SHUT_UP_T <= (NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND Z3_ADR_1 AND NOT Z3_ADR_0 AND
      NOT Z3_ADR(6) AND autoconfig AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5) AND
      SHUT_UP AND NOT Z3_DS/Z3_DS_D2);
SLAVE <= ((FCS)
      OR (NOT lan_adr AND NOT autoconfig));
FDCPE_Z3_ADR2: FDCPE port map (Z3_ADR(2),A(4),NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR3: FDCPE port map (Z3_ADR(3),A(5),NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR4: FDCPE port map (Z3_ADR(4),A(6),NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR5: FDCPE port map (Z3_ADR(5),A(7),NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR6: FDCPE port map (Z3_ADR(6),A(8).PIN,NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR7: FDCPE port map (Z3_ADR(7),A(9).PIN,NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR8: FDCPE port map (Z3_ADR(8),A(10).PIN,NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR9: FDCPE port map (Z3_ADR(9),A(11).PIN,NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR10: FDCPE port map (Z3_ADR(10),A(12).PIN,NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR11: FDCPE port map (Z3_ADR(11),A(13).PIN,NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR12: FDCPE port map (Z3_ADR(12),A(14).PIN,NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR13: FDCPE port map (Z3_ADR(13),A(15).PIN,NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR_0: FDCPE port map (Z3_ADR_0,A(2),NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_ADR_1: FDCPE port map (Z3_ADR_1,A(3),NOT FCS,'0',NOT lan_adr/lan_adr_RSTF);
FDCPE_Z3_A_LOW: FDCPE port map (Z3_A_LOW,Z3_A_LOW_D,CLK_EXT,LAN_SM_RST,'0');
     Z3_A_LOW_D <= ((NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND
      NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$4 AND $OpTx$FX_DC$18)
      OR (NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND
      NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd2 AND $OpTx$FX_DC$18 AND
      NOT $OpTx$FX_SC$29)
      OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd3 AND
      NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
      NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$4)
      OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd3 AND
      NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
      NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_SC$29));
FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),DQ(0).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),DQ(1).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),DQ(2).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),DQ(3).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),DQ(4).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),DQ(5).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),DQ(6).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),DQ(7).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),DQ(8).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),DQ(9).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),DQ(10).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),DQ(11).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),DQ(12).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),DQ(13).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),DQ(14).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),DQ(15).PIN,CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7);
Z3_DS/Z3_DS_D2 <= ($OpTx$FX_DC$4 AND $OpTx$FX_DC$18);
FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,NOT FCS,NOT lan_adr/lan_adr_RSTF,'0');
     autoconfig_D <= (Z3 AND D(9).PIN AND D(8).PIN AND D(14).PIN AND
      D(13).PIN AND D(12).PIN AND D(11).PIN AND D(10).PIN AND D(15).PIN AND
      NOT CFIN AND NOT A(20).PIN AND NOT A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND
      NOT A(16).PIN AND NOT A(23).PIN AND NOT A(22).PIN AND NOT A(21).PIN AND CFOUT);
FDCPE_lan_adr: FDCPE port map (lan_adr,lan_adr_D,NOT FCS,NOT lan_adr/lan_adr_RSTF,'0');
     lan_adr_D <= (Z3 AND NOT D(9).PIN AND NOT D(8).PIN AND D(14).PIN AND
      NOT D(13).PIN AND NOT D(12).PIN AND NOT D(11).PIN AND NOT D(10).PIN AND NOT D(15).PIN AND
      NOT A(20).PIN AND NOT A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND NOT A(16).PIN AND
      NOT A(23).PIN AND NOT A(22).PIN AND NOT A(21).PIN AND NOT SHUT_UP);
lan_adr/lan_adr_RSTF <= (RESET AND BERR);
FDCPE_lan_rdy: FDCPE port map (lan_rdy,lan_rdy_D,CLK_EXT,LAN_SM_RST,'0');
     lan_rdy_D <= ((NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd1 AND
      NOT $OpTx$FX_DC$18)
      OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5 AND
      NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);