cpldfit: version P.68d Xilinx Inc.
Fitter Report
Design Name: LAN_IDE_CP Date: 12-28-2016, 2:13AM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
107/144 ( 74%) 228 /720 ( 32%) 193/432 ( 45%) 22 /144 ( 15%) 107/117 ( 91%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 15/18 26/54 28/90 14/15
FB2 18/18* 26/54 26/90 15/15*
FB3 14/18 26/54 35/90 13/15
FB4 18/18* 26/54 27/90 15/15*
FB5 5/18 17/54 21/90 14/14*
FB6 18/18* 22/54 36/90 13/13*
FB7 14/18 26/54 29/90 12/15
FB8 5/18 24/54 26/90 11/15
----- ----- ----- -----
107/144 193/432 228/720 107/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Signal 'RESET' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 34 34 | I/O : 101 109
Output : 40 40 | GCK/IO : 1 3
Bidirectional : 32 32 | GTS/IO : 4 4
GCK : 0 0 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 107 107
** Power Data **
There are 107 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'LAN_IDE_CP.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
constraint 'P30'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
WARNING:Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be
deleted.
WARNING:Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will
be deleted.
WARNING:Cpld:1007 - Removing unused input(s) 'CLK_EXT'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'DS0'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'DS1'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'FCS'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are
unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'Z3'. The input(s) are unused
after optimization. Please verify functionality via simulation.
************************* Summary of Mapped Logic ************************
** 72 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
IDE_CS<1> 1 1 FB1_1 23 I/O O STD FAST
D<7> 2 3 FB1_2 16 I/O I/O STD FAST
D<1> 2 3 FB1_3 17 I/O I/O STD FAST
IDE_A<2> 1 1 FB1_4 25 I/O O STD FAST
D<8> 2 3 FB1_5 19 I/O I/O STD FAST
D<5> 2 3 FB1_6 20 I/O I/O STD FAST
D<4> 2 3 FB1_8 21 I/O I/O STD FAST
IDE_CS<0> 1 1 FB1_9 22 I/O O STD FAST
IDE_A<0> 1 1 FB1_11 24 I/O O STD FAST
IDE_A<1> 1 1 FB1_12 26 I/O O STD FAST
IDE_R 0 0 FB1_14 27 I/O O STD FAST
IDE_W 0 0 FB1_15 28 I/O O STD FAST
ROM_OE 0 0 FB1_16 35 I/O O STD FAST
A_LAN<9> 1 1 FB2_1 142 I/O O STD FAST
A_LAN<0> 1 1 FB2_4 4 I/O O STD FAST
D<0> 2 3 FB2_5 2 GTS/I/O I/O STD FAST
A_LAN<1> 1 1 FB2_6 3 GTS/I/O O STD FAST
A_LAN<3> 1 1 FB2_8 5 GTS/I/O O STD FAST
A_LAN<2> 1 1 FB2_9 6 GTS/I/O O STD FAST
A_LAN<5> 1 1 FB2_10 7 I/O O STD FAST
A_LAN<4> 1 1 FB2_11 9 I/O O STD FAST
A_LAN<7> 1 1 FB2_12 10 I/O O STD FAST
LAN_CFG<1> 0 0 FB2_13 12 I/O O STD FAST
A_LAN<6> 1 1 FB2_14 11 I/O O STD FAST
LAN_CFG<3> 0 0 FB2_15 13 I/O O STD FAST
D<6> 2 3 FB2_16 14 I/O I/O STD FAST
D<3> 2 3 FB2_17 15 I/O I/O STD FAST
D<2> 2 3 FB3_1 39 I/O I/O STD FAST
INT_OUT 1 1 FB3_2 32 GCK/I/O O STD FAST
D<10> 2 3 FB3_3 41 I/O I/O STD FAST
D<12> 3 4 FB3_4 44 I/O I/O STD FAST
CP_CS 0 0 FB3_6 34 I/O O STD FAST
D<14> 3 4 FB3_7 46 I/O I/O STD FAST
D<9> 2 3 FB3_9 40 I/O I/O STD FAST
D<15> 3 4 FB3_10 48 I/O I/O STD FAST
D<11> 2 3 FB3_11 43 I/O I/O STD FAST
D<13> 3 4 FB3_12 45 I/O I/O STD FAST
DQ<0> 2 3 FB4_1 118 I/O I/O STD FAST
DQ<6> 2 3 FB4_2 126 I/O I/O STD FAST
LAN_CS 0 0 FB4_3 133 I/O O STD FAST
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
DQ<8> 2 3 FB4_5 128 I/O I/O STD FAST
DQ<10> 2 3 FB4_6 129 I/O I/O STD FAST
DQ<12> 2 3 FB4_8 130 I/O I/O STD FAST
DQ<14> 2 3 FB4_9 131 I/O I/O STD FAST
LAN_CFG<2> 0 0 FB4_10 135 I/O O STD FAST
LAN_WRH 1 4 FB4_11 132 I/O O STD FAST
LAN_RD 1 3 FB4_12 134 I/O O STD FAST
A_LAN<12> 1 1 FB4_13 137 I/O O STD FAST
A_LAN<13> 1 1 FB4_14 136 I/O O STD FAST
A_LAN<10> 1 1 FB4_15 138 I/O O STD FAST
A_LAN<11> 1 1 FB4_16 139 I/O O STD FAST
A_LAN<8> 1 1 FB4_17 140 I/O O STD FAST
ROM_B<0> 0 0 FB5_10 68 I/O O STD FAST
CP_WE 0 0 FB5_13 70 I/O O STD FAST
ROM_B<1> 0 0 FB5_17 69 I/O O STD FAST
SLAVE 2 3 FB6_2 106 I/O O STD FAST
LAN_CFG<4> 0 0 FB6_5 110 I/O O STD FAST
DQ<15> 2 3 FB6_6 112 I/O I/O STD FAST
DQ<13> 2 3 FB6_8 113 I/O I/O STD FAST
DQ<9> 2 3 FB6_9 116 I/O I/O STD FAST
DQ<11> 2 3 FB6_10 115 I/O I/O STD FAST
DQ<3> 2 3 FB6_11 119 I/O I/O STD FAST
DQ<2> 2 3 FB6_12 120 I/O I/O STD FAST
DQ<5> 2 3 FB6_14 121 I/O I/O STD FAST
DQ<4> 2 3 FB6_15 124 I/O I/O STD FAST
DQ<1> 2 3 FB6_16 117 I/O I/O STD FAST
DQ<7> 2 3 FB6_17 125 I/O I/O STD FAST
CP_RD 0 0 FB7_2 71 I/O O STD FAST
LAN_WRL 1 4 FB7_6 76 I/O O STD FAST
DTACK 0 0 FB7_12 85 I/O O STD FAST
OWN 1 1 FB8_16 107 I/O O STD FAST
CFOUT 1 3 FB8_17 105 I/O O STD FAST
** 35 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
$OpTx$FX_DC$89 2 4 FB1_17 STD
Dout1<0> 11 14 FB1_18 STD RESET
Dout1_0__or0001/Dout1_0__or0001_D2 2 5 FB2_2 STD
AUTO_CONFIG_DONE_CYCLE<2> 3 15 FB2_3 STD RESET
AUTO_CONFIG_DONE_CYCLE<1> 3 13 FB2_7 STD RESET
$OpTx$FX_DC$87 3 5 FB2_18 STD
$OpTx$FX_DC$93 1 2 FB3_15 STD
$OpTx$FX_DC$92 2 4 FB3_16 STD
$OpTx$FX_DC$108 3 6 FB3_17 STD
Dout1<3> 8 11 FB3_18 STD RESET
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2 2 12 FB4_4 STD
AUTO_CONFIG_DONE_CYCLE<0> 3 13 FB4_7 STD RESET
$OpTx$FX_DC$107 3 5 FB4_18 STD
Dout1<2> 11 14 FB5_1 STD RESET
Dout1<1> 10 13 FB5_16 STD RESET
$OpTx$FX_DC$97 1 4 FB6_1 STD
$OpTx$FX_DC$106 1 3 FB6_3 STD
LAN_BASEADR<7> 3 5 FB6_4 STD RESET
LAN_BASEADR<5> 3 5 FB6_7 STD RESET
LAN_BASEADR<3> 3 5 FB6_13 STD RESET
LAN_BASEADR<1> 3 5 FB6_18 STD RESET
lan/lan_CLKF 2 2 FB7_7 STD
ROM_B_0_OBUF$BUF5/ROM_B_0_OBUF$BUF5_TRST 2 3 FB7_8 STD
AUTO_CONFIG_DONE<2> 2 2 FB7_9 STD RESET
AUTO_CONFIG_DONE<1> 2 2 FB7_10 STD RESET
AUTO_CONFIG_DONE<0> 2 2 FB7_11 STD RESET
SHUT_UP<0> 3 4 FB7_13 STD RESET
LAN_INT_ENABLE 3 5 FB7_14 STD RESET
LAN_BASEADR<6> 3 5 FB7_15 STD RESET
LAN_BASEADR<4> 3 5 FB7_16 STD RESET
LAN_BASEADR<2> 3 5 FB7_17 STD RESET
LAN_BASEADR<0> 3 5 FB7_18 STD RESET
$OpTx$FX_DC$81 1 2 FB8_14 STD
autoconfig 4 14 FB8_15 STD RESET
lan 19 19 FB8_18 STD RESET
** 35 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
CP_IRQ FB1_10 31 I/O I
RESET FB2_2 143 GSR/I/O GSR/I
A<5> FB3_14 49 I/O I
A<4> FB3_15 50 I/O I
A<6> FB3_17 51 I/O I
A<3> FB5_2 52 I/O I
A<10> FB5_3 59 I/O I
A<7> FB5_5 53 I/O I
A<2> FB5_6 54 I/O I
A<14> FB5_7 66 I/O I
A<8> FB5_8 56 I/O I
A<1> FB5_9 57 I/O I
A<9> FB5_11 58 I/O I
A<11> FB5_12 60 I/O I
A<12> FB5_14 61 I/O I
A<13> FB5_15 64 I/O I
LAN_INT FB6_4 111 I/O I
AUTOBOOT_OFF FB7_3 75 I/O I
A<15> FB7_5 74 I/O I
AS FB7_9 80 I/O I
LDS FB7_11 82 I/O I
UDS FB7_13 81 I/O I
A<23> FB7_14 86 I/O I
A<22> FB7_15 87 I/O I
RW FB7_16 83 I/O I
A<21> FB7_17 88 I/O I
A<20> FB8_2 91 I/O I
A<17> FB8_3 95 I/O I
A<16> FB8_4 97 I/O I
A<19> FB8_5 92 I/O I
A<18> FB8_8 94 I/O I
BERR FB8_11 98 I/O I
C1 FB8_13 103 I/O I
C3 FB8_14 102 I/O I
CFIN FB8_15 104 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
IDE_CS<1> 1 0 /\4 0 FB1_1 23 I/O O
D<7> 2 0 0 3 FB1_2 16 I/O I/O
D<1> 2 0 0 3 FB1_3 17 I/O I/O
IDE_A<2> 1 0 0 4 FB1_4 25 I/O O
D<8> 2 0 0 3 FB1_5 19 I/O I/O
D<5> 2 0 0 3 FB1_6 20 I/O I/O
(unused) 0 0 0 5 FB1_7 (b)
D<4> 2 0 0 3 FB1_8 21 I/O I/O
IDE_CS<0> 1 0 0 4 FB1_9 22 I/O O
(unused) 0 0 0 5 FB1_10 31 I/O I
IDE_A<0> 1 0 0 4 FB1_11 24 I/O O
IDE_A<1> 1 0 0 4 FB1_12 26 I/O O
(unused) 0 0 0 5 FB1_13 (b)
IDE_R 0 0 0 5 FB1_14 27 I/O O
IDE_W 0 0 0 5 FB1_15 28 I/O O
ROM_OE 0 0 0 5 FB1_16 35 I/O O
$OpTx$FX_DC$89 2 0 \/2 1 FB1_17 30 GCK/I/O (b)
Dout1<0> 11 6<- 0 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$106 10: A<13> 19: Dout1_0__or0001/Dout1_0__or0001_D2
2: $OpTx$FX_DC$107 11: A<2> 20: LAN_RD
3: $OpTx$FX_DC$81 12: A<3> 21: DQ<8>.PIN
4: $OpTx$FX_DC$87 13: A<4> 22: DQ<7>.PIN
5: $OpTx$FX_DC$93 14: A<5> 23: DQ<5>.PIN
6: AUTOBOOT_OFF 15: A<6> 24: DQ<4>.PIN
7: A<1> 16: A<9> 25: DQ<1>.PIN
8: A<11> 17: A<10> 26: lan/lan_CLKF
9: A<12> 18: Dout1<0>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
IDE_CS<1> .........X.............................. 1
D<7> X..................X.X.................. 3
D<1> X..................X....X............... 3
IDE_A<2> .......X................................ 1
D<8> X..................XX................... 3
D<5> X..................X..X................. 3
D<4> X..................X...X................ 3
IDE_CS<0> ........X............................... 1
IDE_A<0> ...............X........................ 1
IDE_A<1> ................X....................... 1
IDE_R ........................................ 0
IDE_W ........................................ 0
ROM_OE ........................................ 0
$OpTx$FX_DC$89 ...X.......XX.....X..................... 4
Dout1<0> .XXXXXX...XXXXX..XX......X.............. 14
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
A_LAN<9> 1 0 0 4 FB2_1 142 I/O O
Dout1_0__or0001/Dout1_0__or0001_D2
2 0 0 3 FB2_2 143 GSR/I/O GSR/I
AUTO_CONFIG_DONE_CYCLE<2>
3 0 0 2 FB2_3 (b) (b)
A_LAN<0> 1 0 0 4 FB2_4 4 I/O O
D<0> 2 0 0 3 FB2_5 2 GTS/I/O I/O
A_LAN<1> 1 0 0 4 FB2_6 3 GTS/I/O O
AUTO_CONFIG_DONE_CYCLE<1>
3 0 0 2 FB2_7 (b) (b)
A_LAN<3> 1 0 0 4 FB2_8 5 GTS/I/O O
A_LAN<2> 1 0 0 4 FB2_9 6 GTS/I/O O
A_LAN<5> 1 0 0 4 FB2_10 7 I/O O
A_LAN<4> 1 0 0 4 FB2_11 9 I/O O
A_LAN<7> 1 0 0 4 FB2_12 10 I/O O
LAN_CFG<1> 0 0 0 5 FB2_13 12 I/O O
A_LAN<6> 1 0 0 4 FB2_14 11 I/O O
LAN_CFG<3> 0 0 0 5 FB2_15 13 I/O O
D<6> 2 0 0 3 FB2_16 14 I/O I/O
D<3> 2 0 0 3 FB2_17 15 I/O I/O
$OpTx$FX_DC$87 3 0 0 2 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$106 10: A<2> 19: DQ<6>.PIN
2: $OpTx$FX_DC$81 11: A<3> 20: DQ<3>.PIN
3: AS 12: A<4> 21: DQ<0>.PIN
4: AUTO_CONFIG_DONE<0> 13: A<5> 22: RESET
5: AUTO_CONFIG_DONE<1> 14: A<6> 23: RW
6: AUTO_CONFIG_DONE<2> 15: A<7> 24: UDS
7: AUTO_CONFIG_DONE_CYCLE<1> 16: A<8> 25: autoconfig
8: AUTO_CONFIG_DONE_CYCLE<2> 17: A<10> 26: lan/lan_CLKF
9: A<1> 18: LAN_RD
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
A_LAN<9> ................X....................... 1
Dout1_0__or0001/Dout1_0__or0001_D2
X..XXX...............X.................. 5
AUTO_CONFIG_DONE_CYCLE<2>
..XXXX.XX.XXXX.......XXXXX.............. 15
A_LAN<0> ........X............................... 1
D<0> X................X..X................... 3
A_LAN<1> .........X.............................. 1
AUTO_CONFIG_DONE_CYCLE<1>
.XX...X.X.XXXX.......XXXXX.............. 13
A_LAN<3> ...........X............................ 1
A_LAN<2> ..........X............................. 1
A_LAN<5> .............X.......................... 1
A_LAN<4> ............X........................... 1
A_LAN<7> ...............X........................ 1
LAN_CFG<1> ........................................ 0
A_LAN<6> ..............X......................... 1
LAN_CFG<3> ........................................ 0
D<6> X................XX..................... 3
D<3> X................X.X.................... 3
$OpTx$FX_DC$87 .........X.XXX.......X.................. 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
D<2> 2 0 /\2 1 FB3_1 39 I/O I/O
INT_OUT 1 0 0 4 FB3_2 32 GCK/I/O O
D<10> 2 0 0 3 FB3_3 41 I/O I/O
D<12> 3 0 0 2 FB3_4 44 I/O I/O
(unused) 0 0 0 5 FB3_5 33 I/O
CP_CS 0 0 0 5 FB3_6 34 I/O O
D<14> 3 0 0 2 FB3_7 46 I/O I/O
(unused) 0 0 0 5 FB3_8 38 GCK/I/O
D<9> 2 0 0 3 FB3_9 40 I/O I/O
D<15> 3 0 0 2 FB3_10 48 I/O I/O
D<11> 2 0 0 3 FB3_11 43 I/O I/O
D<13> 3 0 0 2 FB3_12 45 I/O I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 49 I/O I
$OpTx$FX_DC$93 1 0 0 4 FB3_15 50 I/O I
$OpTx$FX_DC$92 2 0 0 3 FB3_16 (b) (b)
$OpTx$FX_DC$108 3 0 \/1 1 FB3_17 51 I/O I
Dout1<3> 8 3<- 0 0 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$106 10: A<6> 19: DQ<13>.PIN
2: $OpTx$FX_DC$108 11: Dout1<0> 20: DQ<12>.PIN
3: $OpTx$FX_DC$81 12: Dout1<1> 21: DQ<11>.PIN
4: $OpTx$FX_DC$89 13: Dout1<2> 22: DQ<10>.PIN
5: A<1> 14: Dout1<3> 23: DQ<9>.PIN
6: A<2> 15: Dout1_0__or0001/Dout1_0__or0001_D2 24: DQ<2>.PIN
7: A<3> 16: LAN_RD 25: ROM_B_0_OBUF$BUF5/ROM_B_0_OBUF$BUF5_TRST
8: A<4> 17: DQ<15>.PIN 26: lan/lan_CLKF
9: A<5> 18: DQ<14>.PIN
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
D<2> X..............X.......X................ 3
INT_OUT ........................X............... 1
D<10> X..............X.....X.................. 3
D<12> X.........X....X...X.................... 4
CP_CS ........................................ 0
D<14> X...........X..X.X...................... 4
D<9> X..............X......X................. 3
D<15> X............X.XX....................... 4
D<11> X..............X....X................... 3
D<13> X..........X...X..X..................... 4
$OpTx$FX_DC$93 ..X...X................................. 2
$OpTx$FX_DC$92 ....X.XX......X......................... 4
$OpTx$FX_DC$108 ..XX...XXX....X......................... 6
Dout1<3> .XX.XXXXXX...XX..........X.............. 11
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
DQ<0> 2 0 0 3 FB4_1 118 I/O I/O
DQ<6> 2 0 0 3 FB4_2 126 I/O I/O
LAN_CS 0 0 0 5 FB4_3 133 I/O O
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
2 0 0 3 FB4_4 (b) (b)
DQ<8> 2 0 0 3 FB4_5 128 I/O I/O
DQ<10> 2 0 0 3 FB4_6 129 I/O I/O
AUTO_CONFIG_DONE_CYCLE<0>
3 0 0 2 FB4_7 (b) (b)
DQ<12> 2 0 0 3 FB4_8 130 I/O I/O
DQ<14> 2 0 0 3 FB4_9 131 I/O I/O
LAN_CFG<2> 0 0 0 5 FB4_10 135 I/O O
LAN_WRH 1 0 0 4 FB4_11 132 I/O O
LAN_RD 1 0 0 4 FB4_12 134 I/O O
A_LAN<12> 1 0 0 4 FB4_13 137 I/O O
A_LAN<13> 1 0 0 4 FB4_14 136 I/O O
A_LAN<10> 1 0 0 4 FB4_15 138 I/O O
A_LAN<11> 1 0 0 4 FB4_16 139 I/O O
A_LAN<8> 1 0 0 4 FB4_17 140 I/O O
$OpTx$FX_DC$107 3 0 0 2 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 10: A<3> 19: D<6>.PIN
2: AUTO_CONFIG_DONE<0> 11: A<4> 20: D<8>.PIN
3: AUTO_CONFIG_DONE_CYCLE<0> 12: A<5> 21: RESET
4: A<1> 13: A<6> 22: RW
5: A<11> 14: A<9> 23: UDS
6: A<12> 15: D<0>.PIN 24: autoconfig
7: A<13> 16: D<10>.PIN 25: lan
8: A<14> 17: D<12>.PIN 26: lan/lan_CLKF
9: A<2> 18: D<14>.PIN
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DQ<0> X.............X......X.................. 3
DQ<6> X.................X..X.................. 3
LAN_CS ........................................ 0
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
XX.X....XXXXX.......XXXX................ 12
DQ<8> X..................X.X.................. 3
DQ<10> X..............X.....X.................. 3
AUTO_CONFIG_DONE_CYCLE<0>
XXXX.....XXXX.......XXXX.X.............. 13
DQ<12> X...............X....X.................. 3
DQ<14> X................X...X.................. 3
LAN_CFG<2> ........................................ 0
LAN_WRH X....................XX.X............... 4
LAN_RD X....................X..X............... 3
A_LAN<12> ......X................................. 1
A_LAN<13> .......X................................ 1
A_LAN<10> ....X................................... 1
A_LAN<11> .....X.................................. 1
A_LAN<8> .............X.......................... 1
$OpTx$FX_DC$107 .X......X.XXX........................... 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 17/37
Number of signals used by logic mapping into function block: 17
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Dout1<2> 11 6<- 0 0 FB5_1 (b) (b)
(unused) 0 0 /\1 4 FB5_2 52 I/O I
(unused) 0 0 0 5 FB5_3 59 I/O I
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 53 I/O I
(unused) 0 0 0 5 FB5_6 54 I/O I
(unused) 0 0 0 5 FB5_7 66 I/O I
(unused) 0 0 0 5 FB5_8 56 I/O I
(unused) 0 0 0 5 FB5_9 57 I/O I
ROM_B<0> 0 0 0 5 FB5_10 68 I/O O
(unused) 0 0 0 5 FB5_11 58 I/O I
(unused) 0 0 0 5 FB5_12 60 I/O I
CP_WE 0 0 0 5 FB5_13 70 I/O O
(unused) 0 0 0 5 FB5_14 61 I/O I
(unused) 0 0 \/3 2 FB5_15 64 I/O I
Dout1<1> 10 5<- 0 0 FB5_16 (b) (b)
ROM_B<1> 0 0 /\2 3 FB5_17 69 I/O O
(unused) 0 0 \/5 0 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$108 7: AUTO_CONFIG_DONE<1> 13: A<6>
2: $OpTx$FX_DC$81 8: A<1> 14: Dout1<1>
3: $OpTx$FX_DC$89 9: A<2> 15: Dout1<2>
4: $OpTx$FX_DC$92 10: A<3> 16: Dout1_0__or0001/Dout1_0__or0001_D2
5: $OpTx$FX_DC$93 11: A<4> 17: lan/lan_CLKF
6: AUTO_CONFIG_DONE<0> 12: A<5>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Dout1<2> .XXX.XXXXXXXX.XXX....................... 14
ROM_B<0> ........................................ 0
CP_WE ........................................ 0
Dout1<1> XX.XXXXXX.XX.X.XX....................... 13
ROM_B<1> ........................................ 0
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 22/32
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
$OpTx$FX_DC$97 1 0 0 4 FB6_1 (b) (b)
SLAVE 2 0 0 3 FB6_2 106 I/O O
$OpTx$FX_DC$106 1 0 0 4 FB6_3 (b) (b)
LAN_BASEADR<7> 3 0 0 2 FB6_4 111 I/O I
LAN_CFG<4> 0 0 0 5 FB6_5 110 I/O O
DQ<15> 2 0 0 3 FB6_6 112 I/O I/O
LAN_BASEADR<5> 3 0 0 2 FB6_7 (b) (b)
DQ<13> 2 0 0 3 FB6_8 113 I/O I/O
DQ<9> 2 0 0 3 FB6_9 116 I/O I/O
DQ<11> 2 0 0 3 FB6_10 115 I/O I/O
DQ<3> 2 0 0 3 FB6_11 119 I/O I/O
DQ<2> 2 0 0 3 FB6_12 120 I/O I/O
LAN_BASEADR<3> 3 0 0 2 FB6_13 (b) (b)
DQ<5> 2 0 0 3 FB6_14 121 I/O I/O
DQ<4> 2 0 0 3 FB6_15 124 I/O I/O
DQ<1> 2 0 0 3 FB6_16 117 I/O I/O
DQ<7> 2 0 0 3 FB6_17 125 I/O I/O
LAN_BASEADR<1> 3 0 0 2 FB6_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 9: D<4>.PIN 16: LAN_BASEADR<7>
2: A<15> 10: D<5>.PIN 17: LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
3: D<11>.PIN 11: D<7>.PIN 18: RESET
4: D<13>.PIN 12: D<9>.PIN 19: RW
5: D<15>.PIN 13: LAN_BASEADR<1> 20: autoconfig
6: D<1>.PIN 14: LAN_BASEADR<3> 21: lan
7: D<2>.PIN 15: LAN_BASEADR<5> 22: lan/lan_CLKF
8: D<3>.PIN
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
$OpTx$FX_DC$97 XX................X.X................... 4
SLAVE X..................XX................... 3
$OpTx$FX_DC$106 X.................XX.................... 3
LAN_BASEADR<7> ....X..........XXX...X.................. 5
LAN_CFG<4> ........................................ 0
DQ<15> X...X.............X..................... 3
LAN_BASEADR<5> ...X..........X.XX...X.................. 5
DQ<13> X..X..............X..................... 3
DQ<9> X..........X......X..................... 3
DQ<11> X.X...............X..................... 3
DQ<3> X......X..........X..................... 3
DQ<2> X.....X...........X..................... 3
LAN_BASEADR<3> ..X..........X..XX...X.................. 5
DQ<5> X........X........X..................... 3
DQ<4> X.......X.........X..................... 3
DQ<1> X....X............X..................... 3
DQ<7> X.........X.......X..................... 3
LAN_BASEADR<1> ...........XX...XX...X.................. 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB7_1 (b)
CP_RD 0 0 0 5 FB7_2 71 I/O O
(unused) 0 0 0 5 FB7_3 75 I/O I
(unused) 0 0 0 5 FB7_4 (b)
(unused) 0 0 0 5 FB7_5 74 I/O I
LAN_WRL 1 0 0 4 FB7_6 76 I/O O
lan/lan_CLKF 2 0 0 3 FB7_7 77 I/O (b)
ROM_B_0_OBUF$BUF5/ROM_B_0_OBUF$BUF5_TRST
2 0 0 3 FB7_8 78 I/O (b)
AUTO_CONFIG_DONE<2> 2 0 0 3 FB7_9 80 I/O I
AUTO_CONFIG_DONE<1> 2 0 0 3 FB7_10 79 I/O (b)
AUTO_CONFIG_DONE<0> 2 0 0 3 FB7_11 82 I/O I
DTACK 0 0 0 5 FB7_12 85 I/O O
SHUT_UP<0> 3 0 0 2 FB7_13 81 I/O I
LAN_INT_ENABLE 3 0 0 2 FB7_14 86 I/O I
LAN_BASEADR<6> 3 0 0 2 FB7_15 87 I/O I
LAN_BASEADR<4> 3 0 0 2 FB7_16 83 I/O I
LAN_BASEADR<2> 3 0 0 2 FB7_17 88 I/O I
LAN_BASEADR<0> 3 0 0 2 FB7_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$97 10: D<12>.PIN 19: LAN_INT_ENABLE
2: AS 11: D<14>.PIN 20: LAN_INT
3: AUTO_CONFIG_DONE_CYCLE<0> 12: D<15>.PIN 21: LDS
4: AUTO_CONFIG_DONE_CYCLE<1> 13: D<8>.PIN 22: RESET
5: AUTO_CONFIG_DONE_CYCLE<2> 14: LAN_BASEADR<0> 23: RW
6: C1 15: LAN_BASEADR<2> 24: SHUT_UP<0>
7: C3 16: LAN_BASEADR<4> 25: lan
8: CP_IRQ 17: LAN_BASEADR<6> 26: lan/lan_CLKF
9: D<10>.PIN 18: LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
CP_RD ........................................ 0
LAN_WRL .X..................X.X.X............... 4
lan/lan_CLKF .....XX................................. 2
ROM_B_0_OBUF$BUF5/ROM_B_0_OBUF$BUF5_TRST
.......X..........XX.................... 3
AUTO_CONFIG_DONE<2> .X..X................................... 2
AUTO_CONFIG_DONE<1> .X.X.................................... 2
AUTO_CONFIG_DONE<0> .XX..................................... 2
DTACK ........................................ 0
SHUT_UP<0> .................X...X.X.X.............. 4
LAN_INT_ENABLE X..........X......X..X...X.............. 5
LAN_BASEADR<6> ..........X.....XX...X...X.............. 5
LAN_BASEADR<4> .........X.....X.X...X...X.............. 5
LAN_BASEADR<2> ........X.....X..X...X...X.............. 5
LAN_BASEADR<0> ............XX...X...X...X.............. 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 24/30
Number of signals used by logic mapping into function block: 24
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB8_1 (b) (b)
(unused) 0 0 /\4 1 FB8_2 91 I/O I
(unused) 0 0 0 5 FB8_3 95 I/O I
(unused) 0 0 0 5 FB8_4 97 I/O I
(unused) 0 0 0 5 FB8_5 92 I/O I
(unused) 0 0 0 5 FB8_6 93 I/O
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 94 I/O I
(unused) 0 0 0 5 FB8_9 96 I/O
(unused) 0 0 0 5 FB8_10 101 I/O
(unused) 0 0 0 5 FB8_11 98 I/O I
(unused) 0 0 0 5 FB8_12 100 I/O
(unused) 0 0 0 5 FB8_13 103 I/O I
$OpTx$FX_DC$81 1 0 0 4 FB8_14 102 I/O I
autoconfig 4 0 0 1 FB8_15 104 I/O I
OWN 1 0 \/1 3 FB8_16 107 I/O O
CFOUT 1 1<- \/5 0 FB8_17 105 I/O O
lan 19 14<- 0 0 FB8_18 (b) (b)
Signals Used by Logic in Function Block
1: AUTO_CONFIG_DONE<0> 9: A<21> 17: LAN_BASEADR<3>
2: AUTO_CONFIG_DONE<1> 10: A<22> 18: LAN_BASEADR<4>
3: AUTO_CONFIG_DONE<2> 11: A<23> 19: LAN_BASEADR<5>
4: A<16> 12: BERR 20: LAN_BASEADR<6>
5: A<17> 13: CFIN 21: LAN_BASEADR<7>
6: A<18> 14: LAN_BASEADR<0> 22: SHUT_UP<0>
7: A<19> 15: LAN_BASEADR<1> 23: SLAVE
8: A<20> 16: LAN_BASEADR<2> 24: lan/lan_CLKF
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
$OpTx$FX_DC$81 XX...................................... 2
autoconfig XXXXXXXXXXXXX..........X................ 14
OWN ......................X................. 1
CFOUT XXX..................................... 3
lan ...XXXXXXXXX.XXXXXXXXX.X................ 19
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
$OpTx$FX_DC$106 <= (NOT AS AND RW AND autoconfig);
$OpTx$FX_DC$107 <= ((A(4))
OR (NOT A(2) AND NOT A(6))
OR (AUTO_CONFIG_DONE(0) AND NOT A(5) AND NOT A(6)));
$OpTx$FX_DC$108 <= (($OpTx$FX_DC$89)
OR (A(4) AND A(6) AND NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (A(5) AND NOT $OpTx$FX_DC$81 AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2));
$OpTx$FX_DC$81 <= (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1));
$OpTx$FX_DC$87 <= ((RESET AND NOT A(2) AND NOT A(5))
OR (RESET AND NOT A(5) AND NOT A(6))
OR (RESET AND A(2) AND NOT A(4) AND NOT A(6)));
$OpTx$FX_DC$89 <= ((NOT Dout1_0__or0001/Dout1_0__or0001_D2 AND
NOT $OpTx$FX_DC$87)
OR (NOT A(4) AND A(3) AND NOT Dout1_0__or0001/Dout1_0__or0001_D2));
$OpTx$FX_DC$92 <= ((A(3) AND A(1) AND NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (A(4) AND NOT A(3) AND NOT A(1) AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2));
$OpTx$FX_DC$93 <= (NOT A(3) AND $OpTx$FX_DC$81);
$OpTx$FX_DC$97 <= (NOT AS AND NOT RW AND lan AND A(15));
FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_CYCLE(0),AS,NOT RESET,'0');
FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_CYCLE(1),AS,NOT RESET,'0');
FDCPE_AUTO_CONFIG_DONE2: FDCPE port map (AUTO_CONFIG_DONE(2),AUTO_CONFIG_DONE_CYCLE(2),AS,NOT RESET,'0');
FDCPE_AUTO_CONFIG_DONE_CYCLE0: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_D(0),NOT lan/lan_CLKF,'0','0');
AUTO_CONFIG_DONE_CYCLE_D(0) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(0))
OR (NOT AS AND RESET AND NOT AUTO_CONFIG_DONE(0) AND NOT A(4) AND A(3) AND
NOT A(5) AND NOT A(1) AND NOT RW AND NOT UDS AND autoconfig AND A(6)));
FDCPE_AUTO_CONFIG_DONE_CYCLE1: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_D(1),NOT lan/lan_CLKF,'0','0');
AUTO_CONFIG_DONE_CYCLE_D(1) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(1))
OR (NOT AS AND RESET AND NOT A(4) AND A(3) AND NOT A(5) AND NOT A(1) AND NOT RW AND
NOT UDS AND autoconfig AND A(6) AND $OpTx$FX_DC$81));
FDCPE_AUTO_CONFIG_DONE_CYCLE2: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(2),AUTO_CONFIG_DONE_CYCLE_D(2),NOT lan/lan_CLKF,'0','0');
AUTO_CONFIG_DONE_CYCLE_D(2) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(2))
OR (NOT AS AND RESET AND AUTO_CONFIG_DONE(0) AND
AUTO_CONFIG_DONE(1) AND NOT A(4) AND NOT AUTO_CONFIG_DONE(2) AND A(3) AND NOT A(5) AND
NOT A(1) AND NOT RW AND NOT UDS AND autoconfig AND A(6)));
A_LAN(0) <= A(1);
A_LAN(1) <= A(2);
A_LAN(2) <= A(3);
A_LAN(3) <= A(4);
A_LAN(4) <= A(5);
A_LAN(5) <= A(6);
A_LAN(6) <= A(7);
A_LAN(7) <= A(8);
A_LAN(8) <= A(9);
A_LAN(9) <= A(10);
A_LAN(10) <= A(11);
A_LAN(11) <= A(12);
A_LAN(12) <= A(13);
A_LAN(13) <= A(14);
CFOUT <= NOT ((AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND
AUTO_CONFIG_DONE(2)));
CP_CS <= '0';
CP_RD <= '1';
CP_WE <= '1';
D_I(0) <= NOT ((NOT DQ(0).PIN AND LAN_RD));
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
D_OE(0) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(1) <= NOT ((NOT DQ(1).PIN AND LAN_RD));
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
D_OE(1) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(2) <= NOT ((NOT DQ(2).PIN AND LAN_RD));
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
D_OE(2) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(3) <= NOT ((NOT DQ(3).PIN AND LAN_RD));
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
D_OE(3) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(4) <= NOT ((NOT DQ(4).PIN AND LAN_RD));
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
D_OE(4) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(5) <= NOT ((NOT DQ(5).PIN AND LAN_RD));
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
D_OE(5) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(6) <= NOT ((NOT DQ(6).PIN AND LAN_RD));
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
D_OE(6) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(7) <= NOT ((NOT DQ(7).PIN AND LAN_RD));
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
D_OE(7) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(8) <= NOT ((NOT DQ(8).PIN AND LAN_RD));
D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
D_OE(8) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(9) <= NOT ((NOT DQ(9).PIN AND LAN_RD));
D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
D_OE(9) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(10) <= NOT ((NOT DQ(10).PIN AND LAN_RD));
D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
D_OE(10) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(11) <= NOT ((NOT DQ(11).PIN AND LAN_RD));
D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
D_OE(11) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(12) <= ((Dout1(0) AND NOT LAN_RD)
OR (LAN_RD AND DQ(12).PIN));
D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
D_OE(12) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(13) <= ((Dout1(1) AND NOT LAN_RD)
OR (LAN_RD AND DQ(13).PIN));
D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
D_OE(13) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(14) <= ((Dout1(2) AND NOT LAN_RD)
OR (LAN_RD AND DQ(14).PIN));
D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
D_OE(14) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
D_I(15) <= ((Dout1(3) AND NOT LAN_RD)
OR (LAN_RD AND DQ(15).PIN));
D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
D_OE(15) <= NOT ((NOT LAN_RD AND NOT $OpTx$FX_DC$106));
DQ_I(0) <= D(0).PIN;
DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z';
DQ_OE(0) <= (NOT AS AND NOT RW);
DQ_I(1) <= D(1).PIN;
DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z';
DQ_OE(1) <= (NOT AS AND NOT RW);
DQ_I(2) <= D(2).PIN;
DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z';
DQ_OE(2) <= (NOT AS AND NOT RW);
DQ_I(3) <= D(3).PIN;
DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z';
DQ_OE(3) <= (NOT AS AND NOT RW);
DQ_I(4) <= D(4).PIN;
DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z';
DQ_OE(4) <= (NOT AS AND NOT RW);
DQ_I(5) <= D(5).PIN;
DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z';
DQ_OE(5) <= (NOT AS AND NOT RW);
DQ_I(6) <= D(6).PIN;
DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z';
DQ_OE(6) <= (NOT AS AND NOT RW);
DQ_I(7) <= D(7).PIN;
DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z';
DQ_OE(7) <= (NOT AS AND NOT RW);
DQ_I(8) <= D(8).PIN;
DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z';
DQ_OE(8) <= (NOT AS AND NOT RW);
DQ_I(9) <= D(9).PIN;
DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z';
DQ_OE(9) <= (NOT AS AND NOT RW);
DQ_I(10) <= D(10).PIN;
DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z';
DQ_OE(10) <= (NOT AS AND NOT RW);
DQ_I(11) <= D(11).PIN;
DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z';
DQ_OE(11) <= (NOT AS AND NOT RW);
DQ_I(12) <= D(12).PIN;
DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z';
DQ_OE(12) <= (NOT AS AND NOT RW);
DQ_I(13) <= D(13).PIN;
DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z';
DQ_OE(13) <= (NOT AS AND NOT RW);
DQ_I(14) <= D(14).PIN;
DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z';
DQ_OE(14) <= (NOT AS AND NOT RW);
DQ_I(15) <= D(15).PIN;
DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z';
DQ_OE(15) <= (NOT AS AND NOT RW);
DTACK_I <= '0';
DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
DTACK_OE <= '0';
FDCPE_Dout10: FDCPE port map (Dout1(0),Dout1_D(0),NOT lan/lan_CLKF,'0','0');
Dout1_D(0) <= ((NOT A(3) AND A(1) AND NOT Dout1_0__or0001/Dout1_0__or0001_D2 AND
$OpTx$FX_DC$107)
OR (A(5) AND NOT A(1) AND NOT $OpTx$FX_DC$93 AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (A(2) AND NOT A(5) AND NOT A(1) AND $OpTx$FX_DC$81 AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (NOT A(5) AND NOT AUTOBOOT_OFF AND NOT A(6) AND $OpTx$FX_DC$93 AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (NOT A(2) AND A(4) AND NOT A(3) AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (NOT A(4) AND A(3) AND NOT A(5) AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (Dout1(0) AND Dout1_0__or0001/Dout1_0__or0001_D2)
OR (NOT Dout1_0__or0001/Dout1_0__or0001_D2 AND
NOT $OpTx$FX_DC$87)
OR (A(3) AND A(6) AND NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (A(3) AND NOT $OpTx$FX_DC$81 AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2));
FDCPE_Dout11: FDCPE port map (Dout1(1),Dout1_D(1),NOT lan/lan_CLKF,'0','0');
Dout1_D(1) <= (($OpTx$FX_DC$108)
OR (NOT AUTO_CONFIG_DONE(0) AND A(2) AND A(4) AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (A(4) AND A(1) AND $OpTx$FX_DC$93 AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (A(4) AND NOT A(1) AND NOT $OpTx$FX_DC$81 AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND A(2) AND
A(1) AND NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND $OpTx$FX_DC$81 AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (NOT A(2) AND $OpTx$FX_DC$92)
OR (Dout1(1) AND Dout1_0__or0001/Dout1_0__or0001_D2)
OR (A(5) AND A(1) AND NOT Dout1_0__or0001/Dout1_0__or0001_D2));
FDCPE_Dout12: FDCPE port map (Dout1(2),Dout1_D(2),NOT lan/lan_CLKF,'0','0');
Dout1_D(2) <= (($OpTx$FX_DC$92)
OR ($OpTx$FX_DC$89)
OR (NOT AUTO_CONFIG_DONE(0) AND A(2) AND NOT A(4) AND A(1) AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (AUTO_CONFIG_DONE(1) AND A(5) AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (A(3) AND NOT $OpTx$FX_DC$81 AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (A(5) AND NOT A(1) AND NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (NOT A(2) AND NOT A(1) AND NOT A(6) AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (NOT A(4) AND NOT A(1) AND NOT A(6) AND $OpTx$FX_DC$81 AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (Dout1(2) AND Dout1_0__or0001/Dout1_0__or0001_D2)
OR (NOT A(2) AND A(4) AND NOT Dout1_0__or0001/Dout1_0__or0001_D2));
FDCPE_Dout13: FDCPE port map (Dout1(3),Dout1_D(3),NOT lan/lan_CLKF,'0','0');
Dout1_D(3) <= (($OpTx$FX_DC$108)
OR (A(2) AND NOT A(4) AND A(1) AND $OpTx$FX_DC$81 AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (NOT A(3) AND NOT A(5) AND NOT A(1) AND NOT A(6) AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (A(2) AND NOT A(5) AND NOT A(1) AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (Dout1(3) AND Dout1_0__or0001/Dout1_0__or0001_D2)
OR (A(3) AND NOT $OpTx$FX_DC$81 AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2)
OR (NOT A(2) AND A(3) AND A(1) AND
NOT Dout1_0__or0001/Dout1_0__or0001_D2));
Dout1_0__or0001/Dout1_0__or0001_D2 <= ((RESET AND NOT $OpTx$FX_DC$106)
OR (RESET AND AUTO_CONFIG_DONE(0) AND
AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2)));
IDE_A(0) <= A(9);
IDE_A(1) <= A(10);
IDE_A(2) <= A(11);
IDE_CS(0) <= NOT A(12);
IDE_CS(1) <= NOT A(13);
IDE_R <= '1';
IDE_W <= '1';
INT_OUT_I <= '0';
INT_OUT <= INT_OUT_I when INT_OUT_OE = '1' else 'Z';
INT_OUT_OE <= ROM_B_0_OBUF$BUF5/ROM_B_0_OBUF$BUF5_TRST;
FDCPE_LAN_BASEADR0: FDCPE port map (LAN_BASEADR(0),LAN_BASEADR_D(0),NOT lan/lan_CLKF,'0','0');
LAN_BASEADR_D(0) <= ((NOT LAN_BASEADR(0) AND
NOT LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2)
OR (RESET AND NOT D(8).PIN AND
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2));
FDCPE_LAN_BASEADR1: FDCPE port map (LAN_BASEADR(1),LAN_BASEADR_D(1),NOT lan/lan_CLKF,'0','0');
LAN_BASEADR_D(1) <= ((NOT LAN_BASEADR(1) AND
NOT LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2)
OR (RESET AND NOT D(9).PIN AND
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2));
FDCPE_LAN_BASEADR2: FDCPE port map (LAN_BASEADR(2),LAN_BASEADR_D(2),NOT lan/lan_CLKF,'0','0');
LAN_BASEADR_D(2) <= ((NOT LAN_BASEADR(2) AND
NOT LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2)
OR (RESET AND NOT D(10).PIN AND
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2));
FDCPE_LAN_BASEADR3: FDCPE port map (LAN_BASEADR(3),LAN_BASEADR_D(3),NOT lan/lan_CLKF,'0','0');
LAN_BASEADR_D(3) <= ((NOT LAN_BASEADR(3) AND
NOT LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2)
OR (RESET AND NOT D(11).PIN AND
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2));
FDCPE_LAN_BASEADR4: FDCPE port map (LAN_BASEADR(4),LAN_BASEADR_D(4),NOT lan/lan_CLKF,'0','0');
LAN_BASEADR_D(4) <= ((NOT LAN_BASEADR(4) AND
NOT LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2)
OR (RESET AND NOT D(12).PIN AND
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2));
FDCPE_LAN_BASEADR5: FDCPE port map (LAN_BASEADR(5),LAN_BASEADR_D(5),NOT lan/lan_CLKF,'0','0');
LAN_BASEADR_D(5) <= ((NOT LAN_BASEADR(5) AND
NOT LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2)
OR (RESET AND NOT D(13).PIN AND
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2));
FDCPE_LAN_BASEADR6: FDCPE port map (LAN_BASEADR(6),LAN_BASEADR_D(6),NOT lan/lan_CLKF,'0','0');
LAN_BASEADR_D(6) <= ((NOT LAN_BASEADR(6) AND
NOT LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2)
OR (RESET AND NOT D(14).PIN AND
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2));
FDCPE_LAN_BASEADR7: FDCPE port map (LAN_BASEADR(7),LAN_BASEADR_D(7),NOT lan/lan_CLKF,'0','0');
LAN_BASEADR_D(7) <= ((NOT LAN_BASEADR(7) AND
NOT LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2)
OR (RESET AND NOT D(15).PIN AND
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2));
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2 <= ((NOT RESET)
OR (NOT AS AND NOT AUTO_CONFIG_DONE(0) AND NOT A(2) AND NOT A(4) AND A(3) AND
NOT A(5) AND NOT A(1) AND NOT RW AND NOT UDS AND autoconfig AND A(6)));
LAN_CFG(1) <= '0';
LAN_CFG(2) <= '1';
LAN_CFG(3) <= '0';
LAN_CFG(4) <= '0';
LAN_CS <= '1';
FDCPE_LAN_INT_ENABLE: FDCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_D,NOT lan/lan_CLKF,'0','0');
LAN_INT_ENABLE_D <= ((RESET AND LAN_INT_ENABLE AND NOT $OpTx$FX_DC$97)
OR (RESET AND D(15).PIN AND $OpTx$FX_DC$97));
LAN_RD <= (NOT AS AND RW AND lan);
LAN_WRH <= (NOT AS AND NOT RW AND NOT UDS AND lan);
LAN_WRL <= (NOT AS AND NOT RW AND lan AND NOT LDS);
OWN_I <= '0';
OWN <= OWN_I when OWN_OE = '1' else 'Z';
OWN_OE <= NOT SLAVE;
ROM_B(0) <= '0';
ROM_B(1) <= '0';
ROM_B_0_OBUF$BUF5/ROM_B_0_OBUF$BUF5_TRST <= ((NOT CP_IRQ)
OR (LAN_INT_ENABLE AND NOT LAN_INT));
ROM_OE <= '1';
FDCPE_SHUT_UP0: FDCPE port map (SHUT_UP(0),SHUT_UP_D(0),NOT lan/lan_CLKF,'0','0');
SHUT_UP_D(0) <= ((NOT RESET)
OR (SHUT_UP(0) AND
NOT LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2));
SLAVE <= ((AS)
OR (NOT autoconfig AND NOT lan));
FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,lan/lan_CLKF,'0','0');
autoconfig_D <= ((NOT AUTO_CONFIG_DONE(0) AND BERR AND NOT CFIN AND NOT A(18) AND
A(23) AND NOT A(17) AND NOT A(16) AND A(22) AND A(21) AND A(19) AND NOT A(20))
OR (NOT AUTO_CONFIG_DONE(1) AND BERR AND NOT CFIN AND NOT A(18) AND
A(23) AND NOT A(17) AND NOT A(16) AND A(22) AND A(21) AND A(19) AND NOT A(20))
OR (NOT AUTO_CONFIG_DONE(2) AND BERR AND NOT CFIN AND NOT A(18) AND
A(23) AND NOT A(17) AND NOT A(16) AND A(22) AND A(21) AND A(19) AND NOT A(20)));
FDCPE_lan: FDCPE port map (lan,lan_D,lan/lan_CLKF,'0','0');
lan_D <= ((SHUT_UP(0))
OR (NOT BERR)
OR (EXP14_.EXP)
OR (LAN_BASEADR(3) AND NOT A(19))
OR (NOT LAN_BASEADR(3) AND A(19))
OR (LAN_BASEADR(7) AND NOT A(23))
OR (LAN_BASEADR(1) AND NOT A(17))
OR (NOT LAN_BASEADR(1) AND A(17))
OR (LAN_BASEADR(2) AND NOT A(18))
OR (NOT LAN_BASEADR(2) AND A(18))
OR (LAN_BASEADR(4) AND NOT A(20))
OR (NOT LAN_BASEADR(4) AND A(20))
OR (NOT LAN_BASEADR(7) AND A(23))
OR (LAN_BASEADR(0) AND NOT A(16))
OR (NOT LAN_BASEADR(0) AND A(16)));
lan/lan_CLKF <= C1
XOR
lan/lan_CLKF <= C3;
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-10-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCC
2 D<0> 74 A<15>
3 A_LAN<1> 75 AUTOBOOT_OFF
4 A_LAN<0> 76 LAN_WRL
5 A_LAN<3> 77 TIE
6 A_LAN<2> 78 TIE
7 A_LAN<5> 79 TIE
8 VCC 80 AS
9 A_LAN<4> 81 UDS
10 A_LAN<7> 82 LDS
11 A_LAN<6> 83 RW
12 LAN_CFG<1> 84 VCC
13 LAN_CFG<3> 85 DTACK
14 D<6> 86 A<23>
15 D<3> 87 A<22>
16 D<7> 88 A<21>
17 D<1> 89 GND
18 GND 90 GND
19 D<8> 91 A<20>
20 D<5> 92 A<19>
21 D<4> 93 TIE
22 IDE_CS<0> 94 A<18>
23 IDE_CS<1> 95 A<17>
24 IDE_A<0> 96 TIE
25 IDE_A<2> 97 A<16>
26 IDE_A<1> 98 BERR
27 IDE_R 99 GND
28 IDE_W 100 TIE
29 GND 101 TIE
30 TIE 102 C3
31 CP_IRQ 103 C1
32 INT_OUT 104 CFIN
33 TIE 105 CFOUT
34 CP_CS 106 SLAVE
35 ROM_OE 107 OWN
36 GND 108 GND
37 VCC 109 VCC
38 TIE 110 LAN_CFG<4>
39 D<2> 111 LAN_INT
40 D<9> 112 DQ<15>
41 D<10> 113 DQ<13>
42 VCC 114 GND
43 D<11> 115 DQ<11>
44 D<12> 116 DQ<9>
45 D<13> 117 DQ<1>
46 D<14> 118 DQ<0>
47 GND 119 DQ<3>
48 D<15> 120 DQ<2>
49 A<5> 121 DQ<5>
50 A<4> 122 TDO
51 A<6> 123 GND
52 A<3> 124 DQ<4>
53 A<7> 125 DQ<7>
54 A<2> 126 DQ<6>
55 VCC 127 VCC
56 A<8> 128 DQ<8>
57 A<1> 129 DQ<10>
58 A<9> 130 DQ<12>
59 A<10> 131 DQ<14>
60 A<11> 132 LAN_WRH
61 A<12> 133 LAN_CS
62 GND 134 LAN_RD
63 TDI 135 LAN_CFG<2>
64 A<13> 136 A_LAN<13>
65 TMS 137 A_LAN<12>
66 A<14> 138 A_LAN<10>
67 TCK 139 A_LAN<11>
68 ROM_B<0> 140 A_LAN<8>
69 ROM_B<1> 141 VCC
70 CP_WE 142 A_LAN<9>
71 CP_RD 143 RESET
72 GND 144 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-10-TQ144
Optimization Method : DENSITY
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : FLOAT
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 10