Timing Report

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Design Name LAN_IDE_CP
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Thu Dec 15 19:17:49 2016
Created By Timing Report Generator: version P.68d
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_ENABLE.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'SHUT_UP<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'ide.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'autoconfig.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_R.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'IDE_W.CLKF' has multiple original clock nets 'C1' 'C3'.
Possible asynchronous logic: Clock pin 'ROM_OE.CLKF' has multiple original clock nets 'C1' 'C3'.

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for C1
Clock to Setup (tCYC) 11.400 ns.
Pad to Pad Delay (tPD) 10.000 ns.
Setup to Clock at the Pad (tSU) -4.200 ns.
Clock Pad to Output Pad Delay (tCO) 17.900 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
AUTO_TS_F2F 0.0 11.4 59 59
AUTO_TS_P2P 0.0 17.9 11 11
AUTO_TS_P2F 0.0 13.9 171 171
AUTO_TS_F2P 0.0 4.0 3 3


Constraint: TS1000

Description: PERIOD:PERIOD_C1:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_C3:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_AS:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
IDE_BASEADR<4>.Q to ide.D 0.000 11.400 -11.400
IDE_BASEADR<5>.Q to ide.D 0.000 11.400 -11.400
IDE_BASEADR<0>.Q to ide.D 0.000 11.000 -11.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
C1 to IDE_R 0.000 17.900 -17.900
C1 to IDE_W 0.000 17.900 -17.900
C1 to ROM_OE 0.000 17.900 -17.900


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
C1 to AUTO_CONFIG_DONE_CYCLE<1>.CLKF 0.000 13.900 -13.900
C1 to IDE_BASEADR<0>.CLKF 0.000 13.900 -13.900
C1 to IDE_BASEADR<1>.CLKF 0.000 13.900 -13.900


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
IDE_R.Q to IDE_R 0.000 4.000 -4.000
IDE_W.Q to IDE_W 0.000 4.000 -4.000
ROM_OE.Q to ROM_OE 0.000 4.000 -4.000



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
C1 71.429 Limited by Clock Pulse Width for C1
C3 71.429 Limited by Clock Pulse Width for C3
AS 71.429 Limited by Clock Pulse Width for AS

Setup/Hold Times for Clocks

Setup/Hold Times for Clock C1
Source Pad Setup to clk (edge) Hold to clk (edge)
A<16> -4.600 9.100
A<17> -4.600 9.100
A<18> -4.600 9.100
A<19> -5.600 9.100
A<1> -5.600 9.100
A<20> -4.200 9.100
A<21> -4.200 9.100
A<22> -4.600 9.100
A<23> -4.600 9.100
A<2> -5.600 9.100
A<3> -5.600 9.100
A<4> -5.600 9.100
A<5> -5.600 9.100
A<6> -5.600 9.100
AS -5.600 9.100
BERR -5.600 9.100
D<10> -5.600 9.100
D<11> -5.600 9.100
D<12> -5.600 9.100
D<13> -5.600 9.100
D<14> -5.600 9.100
D<15> -5.600 9.100
D<8> -5.600 9.100
D<9> -5.600 9.100
RESET -5.600 9.100
RW -5.600 9.100
UDS -5.600 9.100

Setup/Hold Times for Clock C3
Source Pad Setup to clk (edge) Hold to clk (edge)
A<16> -4.600 9.100
A<17> -4.600 9.100
A<18> -4.600 9.100
A<19> -5.600 9.100
A<1> -5.600 9.100
A<20> -4.200 9.100
A<21> -4.200 9.100
A<22> -4.600 9.100
A<23> -4.600 9.100
A<2> -5.600 9.100
A<3> -5.600 9.100
A<4> -5.600 9.100
A<5> -5.600 9.100
A<6> -5.600 9.100
AS -5.600 9.100
BERR -5.600 9.100
D<10> -5.600 9.100
D<11> -5.600 9.100
D<12> -5.600 9.100
D<13> -5.600 9.100
D<14> -5.600 9.100
D<15> -5.600 9.100
D<8> -5.600 9.100
D<9> -5.600 9.100
RESET -5.600 9.100
RW -5.600 9.100
UDS -5.600 9.100


Clock to Pad Timing

Clock C1 to Pad
Destination Pad Clock (edge) to Pad
IDE_R 17.900
IDE_W 17.900
ROM_OE 17.900

Clock C3 to Pad
Destination Pad Clock (edge) to Pad
IDE_R 17.900
IDE_W 17.900
ROM_OE 17.900


Clock to Setup Times for Clocks

Clock to Setup for clock C1
Source Destination Delay
IDE_BASEADR<4>.Q ide.D 11.400
IDE_BASEADR<5>.Q ide.D 11.400
IDE_BASEADR<0>.Q ide.D 11.000
IDE_BASEADR<1>.Q ide.D 11.000
IDE_BASEADR<2>.Q ide.D 11.000
IDE_BASEADR<6>.Q ide.D 11.000
IDE_BASEADR<7>.Q ide.D 11.000
AUTO_CONFIG_DONE_CYCLE<1>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 10.000
IDE_BASEADR<0>.Q IDE_BASEADR<0>.D 10.000
IDE_BASEADR<1>.Q IDE_BASEADR<1>.D 10.000
IDE_BASEADR<2>.Q IDE_BASEADR<2>.D 10.000
IDE_BASEADR<3>.Q IDE_BASEADR<3>.D 10.000
IDE_BASEADR<3>.Q ide.D 10.000
IDE_BASEADR<4>.Q IDE_BASEADR<4>.D 10.000
IDE_BASEADR<5>.Q IDE_BASEADR<5>.D 10.000
IDE_BASEADR<6>.Q IDE_BASEADR<6>.D 10.000
IDE_BASEADR<7>.Q IDE_BASEADR<7>.D 10.000
IDE_ENABLE.Q IDE_ENABLE.D 10.000
IDE_ENABLE.Q IDE_R.D 10.000
IDE_ENABLE.Q ROM_OE.D 10.000
SHUT_UP<1>.Q SHUT_UP<1>.D 10.000
SHUT_UP<1>.Q ide.D 10.000
autoconfig.Q AUTO_CONFIG_DONE_CYCLE<1>.D 10.000
autoconfig.Q IDE_BASEADR<0>.D 10.000
autoconfig.Q IDE_BASEADR<1>.D 10.000
autoconfig.Q IDE_BASEADR<2>.D 10.000
autoconfig.Q IDE_BASEADR<3>.D 10.000
autoconfig.Q IDE_BASEADR<4>.D 10.000
autoconfig.Q IDE_BASEADR<5>.D 10.000
autoconfig.Q IDE_BASEADR<6>.D 10.000
autoconfig.Q IDE_BASEADR<7>.D 10.000
autoconfig.Q SHUT_UP<1>.D 10.000
ide.Q IDE_ENABLE.D 10.000
ide.Q IDE_R.D 10.000
ide.Q IDE_W.D 10.000
ide.Q ROM_OE.D 10.000

Clock to Setup for clock C3
Source Destination Delay
IDE_BASEADR<4>.Q ide.D 11.400
IDE_BASEADR<5>.Q ide.D 11.400
IDE_BASEADR<0>.Q ide.D 11.000
IDE_BASEADR<1>.Q ide.D 11.000
IDE_BASEADR<2>.Q ide.D 11.000
IDE_BASEADR<6>.Q ide.D 11.000
IDE_BASEADR<7>.Q ide.D 11.000
AUTO_CONFIG_DONE_CYCLE<1>.Q AUTO_CONFIG_DONE_CYCLE<1>.D 10.000
IDE_BASEADR<0>.Q IDE_BASEADR<0>.D 10.000
IDE_BASEADR<1>.Q IDE_BASEADR<1>.D 10.000
IDE_BASEADR<2>.Q IDE_BASEADR<2>.D 10.000
IDE_BASEADR<3>.Q IDE_BASEADR<3>.D 10.000
IDE_BASEADR<3>.Q ide.D 10.000
IDE_BASEADR<4>.Q IDE_BASEADR<4>.D 10.000
IDE_BASEADR<5>.Q IDE_BASEADR<5>.D 10.000
IDE_BASEADR<6>.Q IDE_BASEADR<6>.D 10.000
IDE_BASEADR<7>.Q IDE_BASEADR<7>.D 10.000
IDE_ENABLE.Q IDE_ENABLE.D 10.000
IDE_ENABLE.Q IDE_R.D 10.000
IDE_ENABLE.Q ROM_OE.D 10.000
SHUT_UP<1>.Q SHUT_UP<1>.D 10.000
SHUT_UP<1>.Q ide.D 10.000
autoconfig.Q AUTO_CONFIG_DONE_CYCLE<1>.D 10.000
autoconfig.Q IDE_BASEADR<0>.D 10.000
autoconfig.Q IDE_BASEADR<1>.D 10.000
autoconfig.Q IDE_BASEADR<2>.D 10.000
autoconfig.Q IDE_BASEADR<3>.D 10.000
autoconfig.Q IDE_BASEADR<4>.D 10.000
autoconfig.Q IDE_BASEADR<5>.D 10.000
autoconfig.Q IDE_BASEADR<6>.D 10.000
autoconfig.Q IDE_BASEADR<7>.D 10.000
autoconfig.Q SHUT_UP<1>.D 10.000
ide.Q IDE_ENABLE.D 10.000
ide.Q IDE_R.D 10.000
ide.Q IDE_W.D 10.000
ide.Q ROM_OE.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
A<10> IDE_A<1> 10.000
A<11> IDE_A<2> 10.000
A<12> IDE_CS<0> 10.000
A<13> IDE_CS<1> 10.000
A<9> IDE_A<0> 10.000


Number of paths analyzed: 244
Number of Timing errors: 244
Analysis Completed: Thu Dec 15 19:17:49 2016