| Design Name | LAN_IDE_CP |
| Fitting Status | Design Rule Checking Failed |
| Software Version | P.68d |
| Device Used | XC95144XL-10-TQ144 |
| Date | 12-29-2016, 2:55PM |
| Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
|---|---|---|---|---|
| 72/144 (50%) | 147/720 (21%) | 4/144 (3%) | 105/117 (90%) | 120/432 (28%) |
|
|
| Global clock net(s) used | 0 |
| Global output enable net(s) used | 0 |
| Global set/rest net(s) used | 0 |
| Macrocells in high performance mode (MCHP) | 72 |
| Macrocells in low power mode (MCLP) | 0 |
| Total macrocells used (MC) | 72 |