| Design Name | LAN_IDE_CP |
| Fitting Status | Successful |
| Software Version | P.20131013 |
| Device Used | XC95288XL-10-TQ144 |
| Date | 12-21-2017, 9:41PM |
| Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
|---|---|---|---|---|
| 139/288 (49%) | 709/1440 (50%) | 57/288 (20%) | 111/117 (95%) | 417/864 (49%) |
|
|
| Signal mapped onto global clock net (GCK1) | CLK_EXT |
| Signal mapped onto global output enable net (GSR) | RESET |
| Macrocells in high performance mode (MCHP) | 139 |
| Macrocells in low power mode (MCLP) | 0 |
| Total macrocells used (MC) | 139 |