Logic

Signal Name Total Pterms Total Inputs Function Block Macrocell Power Mode Slew Rate Pin Number Pin Type Pin Use Reg Init State
N0$BUF7/N0$BUF7_TRST__$INT 2 4 FB1 MC1 STD     (b) (b)  
LAN_WR_RST 2 3 FB1 MC2 STD     (b) (b) RESET
LAN_RST_SM_FSM_FFd1 2 4 FB1 MC3 STD     (b) (b) RESET
LAN_IRQ_D0 2 2 FB1 MC4 STD     (b) (b) RESET
D<5> 5 9 FB1 MC5 STD FAST 20 I/O I/O  
D<4> 5 9 FB1 MC6 STD FAST 21 I/O I/O  
LAN_CS_RST 2 3 FB1 MC7 STD     (b) (b) RESET
IDE_CS<0> 0 0 FB1 MC8 STD FAST 22 I/O O  
LAN_RST_SM_FSM_FFd2 3 4 FB1 MC9 STD     (b) (b) RESET
IDE_CS<1> 0 0 FB1 MC10 STD FAST 23 I/O O  
D_OUT<7> 5 12 FB1 MC11 STD     (b) (b) SET
IDE_A<0> 0 0 FB1 MC12 STD FAST 24 I/O O  
D_OUT<3> 5 11 FB1 MC13 STD     (b) (b) SET
IDE_A<2> 0 0 FB1 MC14 STD FAST 25 I/O O  
IDE_A<1> 0 0 FB1 MC15 STD FAST 26 I/O O  
CONFIG_READY 5 9 FB1 MC16 STD     (b) (b) RESET
IDE_R 0 0 FB1 MC17 STD FAST 27 I/O O  
LAN_IRQ_OUT 10 13 FB1 MC18 STD     (b) (b) RESET
DQ_DATA<1> 13 13 FB10 MC1 STD     (b) (b) RESET
DQ<1> 3 4 FB10 MC2 STD FAST 117 I/O I/O  
DQ<0> 2 3 FB10 MC3 STD FAST 118 I/O I/O  
LAN_D_INIT<1> 2 2 FB10 MC4 STD     (b) (b) RESET
DQ<3> 2 3 FB10 MC5 STD FAST 119 I/O I/O  
DQ<2> 2 3 FB10 MC6 STD FAST 120 I/O I/O  
LAN_A_INIT<6> 2 2 FB10 MC7 STD     (b) (b) SET
DQ<5> 2 3 FB10 MC8 STD FAST 121 I/O I/O  
DQ_DATA<9> 13 13 FB10 MC9 STD     (b) (b) RESET
DQ<4> 3 4 FB10 MC10 STD FAST 124 I/O I/O  
DQ<7> 2 3 FB10 MC11 STD FAST 125 I/O I/O  
DQ<6> 2 3 FB10 MC12 STD FAST 126 I/O I/O  
LAN_RST_SM_FSM_FFd3 3 3 FB10 MC13 STD     (b) (b) RESET
DQ<8> 3 4 FB10 MC14 STD FAST 128 I/O I/O  
DQ_DATA<8> 13 13 FB10 MC15 STD     (b) (b) RESET
DQ<10> 3 4 FB10 MC17 STD FAST 129 I/O I/O  
LAN_D_INIT<8> 2 2 FB10 MC18 STD     (b) (b) RESET
Z3_DATA<30> 4 8 FB11 MC1 STD     (b) (b) RESET
A<11> 5 11 FB11 MC3 STD FAST 60 I/O I/O RESET
Z3_DATA<22> 4 8 FB11 MC4 STD     (b) (b) RESET
A<12> 5 11 FB11 MC5 STD FAST 61 I/O I/O RESET
Z3_DATA<21> 4 8 FB11 MC6 STD     (b) (b) RESET
LAN_SM_FSM_FFd2 6 12 FB11 MC7 STD     (b) (b) RESET
LAN_RD_S 7 12 FB11 MC9 STD     (b) (b) RESET
A<13> 5 11 FB11 MC10 STD FAST 64 I/O I/O RESET
A<14> 5 11 FB11 MC11 STD FAST 66 I/O I/O RESET
ROM_B<0> 0 0 FB11 MC12 STD FAST 68 I/O O  
Z3_A_LOW 11 11 FB11 MC13 STD     (b) (b) RESET
ROM_B<1> 0 0 FB11 MC14 STD FAST 69 I/O O  
DQ_DATA<0> 13 13 FB11 MC16 STD     (b) (b) RESET
CP_WE 0 0 FB11 MC17 STD FAST 70 I/O O  
Z3_DATA<29> 4 8 FB11 MC18 STD     (b) (b) RESET
LAN_CFG<4> 0 0 FB12 MC2 STD FAST 110 I/O O  
DQ<15> 2 3 FB12 MC5 STD FAST 112 I/O I/O  
DQ<13> 2 3 FB12 MC8 STD FAST 113 I/O I/O  
DQ<11> 3 4 FB12 MC10 STD FAST 115 I/O I/O  
DQ<9> 3 4 FB12 MC12 STD FAST 116 I/O I/O  
Z3_ADR_1/Z3_ADR_1_SETF__$INT 1 2 FB12 MC13 STD     (b) (b)  
Z3_ADR<5> 3 3 FB12 MC14 STD     (b) (b) RESET
Z3_ADR<4> 3 3 FB12 MC15 STD     (b) (b) RESET
Z3_ADR<3> 3 3 FB12 MC16 STD     (b) (b) RESET
Z3_ADR<2> 3 3 FB12 MC17 STD     (b) (b) RESET
AUTOCONFIG_ACCESS 3 21 FB12 MC18 STD     (b) (b) RESET
LAN_A_INIT<3> 1 1 FB13 MC1 STD     (b) (b) SET
CP_RD 0 0 FB13 MC2 STD FAST 71 I/O O  
DQ_DATA<7> 13 13 FB13 MC5 STD     (b) (b) RESET
LAN_INT_ENABLE 7 10 FB13 MC6 STD     (b) (b) RESET
A<15> 5 11 FB13 MC8 STD FAST 74 I/O I/O RESET
DQ_DATA<6> 13 13 FB13 MC10 STD     (b) (b) RESET
LAN_SM_RST 3 6 FB13 MC11 STD   75 I/O I RESET
LAN_WRL 3 4 FB13 MC14 STD FAST 76 I/O O  
DQ_DATA<15> 13 13 FB13 MC15 STD   77 I/O I RESET
DQ_DATA<14> 13 13 FB13 MC18 STD     (b) (b) RESET
OVR 0 0 FB14 MC3 STD FAST 100 I/O O  
CFOUT 3 4 FB14 MC11 STD FAST 105 I/O O SET
SLAVE 2 3 FB14 MC14 STD FAST 106 I/O O  
OWN 0 0 FB14 MC15 STD FAST 107 I/O O  
DQ_DATA<10> 13 13 FB15 MC1 STD     (b) (b) RESET
LAN_WRL_S 3 7 FB15 MC2 STD   79 I/O I RESET
LAN_WRH_S 3 7 FB15 MC3 STD   80 I/O (b) RESET
Z3_DATA<31> 4 8 FB15 MC4 STD     (b) (b) RESET
DQ_DATA<3> 13 13 FB15 MC7 STD     (b) (b) RESET
DQ_DATA<2> 13 13 FB15 MC8 STD   81 I/O I RESET
DQ_DATA<11> 13 13 FB15 MC11 STD   83 I/O I RESET
DTACK 1 1 FB15 MC12 STD FAST 85 I/O O  
Z3_DATA<23> 4 8 FB15 MC13 STD     (b) (b) RESET
A<23> 5 11 FB15 MC14 STD FAST 86 I/O I/O RESET
A<22> 5 11 FB15 MC15 STD FAST 87 I/O I/O RESET
LAN_READY 5 7 FB15 MC16 STD     (b) (b) RESET
A<21> 5 11 FB15 MC17 STD FAST 88 I/O I/O RESET
Z3_DATA<28> 4 8 FB16 MC1 STD     (b) (b) RESET
A<20> 5 11 FB16 MC2 STD FAST 91 I/O I/O RESET
A<19> 5 11 FB16 MC3 STD FAST 92 I/O I/O RESET
Z3_DATA<27> 4 8 FB16 MC4 STD     (b) (b) RESET
Z3_DATA<26> 4 8 FB16 MC5 STD   93 I/O I RESET
A<18> 5 11 FB16 MC6 STD FAST 94 I/O I/O RESET
Z3_DATA<25> 4 8 FB16 MC7 STD     (b) (b) RESET
A<17> 5 11 FB16 MC8 STD FAST 95 I/O I/O RESET
Z3_DATA<24> 4 8 FB16 MC9 STD     (b) (b) RESET
MTACK 0 0 FB16 MC10 STD FAST 96 I/O O  
A<16> 5 11 FB16 MC11 STD FAST 97 I/O I/O RESET
Z3_DATA<20> 4 8 FB16 MC12 STD   98 I/O I RESET
LAN_SM_FSM_FFd3 10 12 FB16 MC13 STD     (b) (b) RESET
Z3_DATA<19> 4 8 FB16 MC14 STD     (b) (b) RESET
Z3_DATA<18> 4 8 FB16 MC15 STD     (b) (b) RESET
Z3_DATA<17> 4 8 FB16 MC16 STD     (b) (b) RESET
Z3_DATA<16> 4 8 FB16 MC17 STD     (b) (b) RESET
LAN_SM_FSM_FFd4 10 12 FB16 MC18 STD     (b) (b) RESET
LAN_BASEADR<0> 9 17 FB2 MC1 STD     (b) (b) RESET
A_LAN<4> 1 2 FB2 MC2 STD FAST 9 I/O O  
A_LAN<7> 1 2 FB2 MC3 STD FAST 10 I/O O  
LAN_BASEADR<11> 9 17 FB2 MC4 STD     (b) (b) RESET
A_LAN<6> 2 3 FB2 MC5 STD FAST 11 I/O O  
LAN_CFG<1> 0 0 FB2 MC6 STD FAST 12 I/O O  
LAN_BASEADR<12> 9 17 FB2 MC7 STD     (b) (b) RESET
LAN_CFG<3> 0 0 FB2 MC8 STD FAST 13 I/O O  
SHUT_UP 5 16 FB2 MC9 STD     (b) (b) RESET
D<6> 5 9 FB2 MC10 STD FAST 14 I/O I/O  
D<3> 5 9 FB2 MC12 STD FAST 15 I/O I/O  
D<7> 5 9 FB2 MC14 STD FAST 16 I/O I/O  
D<1> 5 9 FB2 MC15 STD FAST 17 I/O I/O  
LAN_BASEADR<10> 9 17 FB2 MC16 STD     (b) (b) RESET
D<8> 9 10 FB2 MC17 STD FAST 19 I/O I/O  
IDE_W 0 0 FB3 MC2 STD FAST 28 I/O O  
INT_OUT 1 2 FB3 MC14 STD FAST 32 I/O/GCK2 O  
D<0> 5 9 FB4 MC2 STD FAST 2 I/O/GTS3 I/O  
$OpTx$FX_DC$110 2 5 FB4 MC3 STD     (b) (b)  
LAN_BASEADR<6> 9 17 FB4 MC4 STD     (b) (b) RESET
A_LAN<1> 1 2 FB4 MC5 STD FAST 3 I/O/GTS4 O  
A_LAN<0> 1 2 FB4 MC6 STD FAST 4 I/O O  
LAN_BASEADR<5> 9 17 FB4 MC7 STD     (b) (b) RESET
A_LAN<3> 2 3 FB4 MC8 STD FAST 5 I/O/GTS1 O  
LAN_BASEADR<3> 9 17 FB4 MC9 STD     (b) (b) RESET
LAN_BASEADR<4> 9 17 FB4 MC10 STD     (b) (b) RESET
A_LAN<2> 1 2 FB4 MC12 STD FAST 6 I/O/GTS2 O  
LAN_BASEADR<2> 9 17 FB4 MC13 STD     (b) (b) RESET
A_LAN<5> 1 2 FB4 MC14 STD FAST 7 I/O O  
LAN_BASEADR<1> 9 17 FB4 MC15 STD     (b) (b) RESET
D_OUT<5> 12 14 FB4 MC17 STD     (b) (b) SET
D_OUT<4> 11 14 FB4 MC18 STD     (b) (b) SET
AUTO_CONFIG_DONE_CYCLE 5 15 FB5 MC1 STD     (b) (b) RESET
CP_CS 0 0 FB5 MC2 STD FAST 34 I/O O  
LAN_BASEADR<13> 9 17 FB5 MC4 STD     (b) (b) RESET
ROM_OE 0 0 FB5 MC5 STD FAST 35 I/O O  
LAN_BASEADR<14> 9 17 FB5 MC7 STD     (b) (b) RESET
LAN_BASEADR<15> 9 17 FB5 MC8 STD   38 I/O/GCK3 (b) RESET
D<2> 5 9 FB5 MC10 STD FAST 39 I/O I/O  
D<9> 9 10 FB5 MC12 STD FAST 40 I/O I/O  
D<10> 9 10 FB5 MC14 STD FAST 41 I/O I/O  
D<11> 9 10 FB5 MC15 STD FAST 43 I/O I/O  
D<12> 9 10 FB5 MC17 STD FAST 44 I/O I/O  
$OpTx$FX_DC$116__$INT 4 8 FB5 MC18 STD     (b) (b)  
$OpTx$INV$203 16 16 FB6 MC1 STD     (b) (b)  
LAN_CFG<2> 0 0 FB6 MC2 STD FAST 135 I/O O  
A_LAN<12> 1 2 FB6 MC3 STD FAST 136 I/O O  
A_LAN<13> 1 2 FB6 MC5 STD FAST 137 I/O O  
A_LAN<10> 1 2 FB6 MC6 STD FAST 138 I/O O  
A_LAN<11> 1 2 FB6 MC8 STD FAST 139 I/O O  
A_LAN<8> 1 2 FB6 MC10 STD FAST 140 I/O O  
Z3_ADR_1 3 3 FB6 MC11 STD     (b) (b) RESET
Z3_ADR_0 3 3 FB6 MC12 STD     (b) (b) RESET
Z3_ADR<9> 3 3 FB6 MC13 STD     (b) (b) RESET
A_LAN<9> 1 2 FB6 MC14 STD FAST 142 I/O O  
Z3_ADR<8> 3 3 FB6 MC15 STD   143 I/O/GSR I RESET
Z3_ADR<7> 3 3 FB6 MC16 STD     (b) (b) RESET
Z3_ADR<6> 3 3 FB6 MC17 STD     (b) (b) RESET
D_OUT<6> 11 14 FB7 MC2 STD     (b) (b) SET
D<13> 9 10 FB7 MC3 STD FAST 45 I/O I/O  
D<14> 9 10 FB7 MC5 STD FAST 46 I/O I/O  
D_OUT<1> 10 13 FB7 MC8 STD     (b) (b) SET
D_OUT<2> 9 13 FB7 MC10 STD     (b) (b) SET
D<15> 9 10 FB7 MC12 STD FAST 48 I/O I/O  
LAN_BASEADR<7> 9 17 FB7 MC13 STD     (b) (b) RESET
LAN_BASEADR<8> 9 17 FB7 MC14 STD     (b) (b) RESET
LAN_BASEADR<9> 9 17 FB7 MC16 STD     (b) (b) RESET
D_OUT<0> 5 13 FB7 MC18 STD     (b) (b) SET
DQ<12> 2 3 FB8 MC2 STD FAST 130 I/O I/O  
DQ<14> 2 3 FB8 MC3 STD FAST 131 I/O I/O  
Z3_ADR<13> 3 3 FB8 MC4 STD     (b) (b) RESET
LAN_WRH 3 4 FB8 MC5 STD FAST 132 I/O O  
Z3_ADR<12> 3 3 FB8 MC7 STD     (b) (b) RESET
LAN_CS 2 3 FB8 MC8 STD FAST 133 I/O O  
Z3_ADR<11> 3 3 FB8 MC9 STD     (b) (b) RESET
LAN_RD 1 3 FB8 MC10 STD FAST 134 I/O O  
Z3_ADR<10> 3 3 FB8 MC11 STD     (b) (b) RESET
LAN_ACCESS 21 21 FB8 MC13 STD     (b) (b) RESET
DQ_SWAP 23 23 FB8 MC18 STD     (b) (b) RESET
$OpTx$FX_SC$117__$INT 4 8 FB9 MC1 STD     (b) (b)  
DQ_DATA<4> 13 13 FB9 MC2 STD   50 I/O I RESET
DQ_DATA<5> 13 13 FB9 MC4 STD     (b) (b) RESET
DQ_DATA<13> 13 13 FB9 MC8 STD   54 I/O I RESET
A<8> 5 11 FB9 MC11 STD FAST 56 I/O I/O RESET
DQ_DATA<12> 13 13 FB9 MC12 STD   57 I/O (b) RESET
A<9> 5 11 FB9 MC14 STD FAST 58 I/O I/O RESET
A<10> 5 11 FB9 MC17 STD FAST 59 I/O I/O RESET
LAN_SM_FSM_FFd1 4 6 FB9 MC18 STD     (b) (b) RESET