Timing Report

Need help reading this report?

Design Name	LAN_IDE_CP
Device, Speed (SpeedFile Version)	XC95144XL, -10 (3.0)
Date Created	Wed Dec 28 23:10:11 2016
Created By	Timing Report Generator: version P.68d
Copyright	Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'D<12>_BUFR.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'D<13>_BUFR.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'D<14>_BUFR.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'D<15>_BUFR.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'ide.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'autoconfig.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<0>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<1>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<2>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_ENABLE.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<0>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<1>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<2>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<3>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<4>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<5>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<6>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_BASEADR<7>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'SHUT_UP<1>.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_R.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'IDE_W.CLKF' has multiple original clock nets 'C3' 'C1'.
Possible asynchronous logic: Clock pin 'ROM_OE.CLKF' has multiple original clock nets 'C3' 'C1'.

Performance Summary
Min. Clock Period	18.700 ns.
Max. Clock Frequency (fSYSTEM)	53.476 MHz.
Limited by Cycle Time for C3
Clock to Setup (tCYC)	18.700 ns.
Pad to Pad Delay (tPD)	18.700 ns.
Setup to Clock at the Pad (tSU)	-4.200 ns.
Clock Pad to Output Pad Delay (tCO)	34.300 ns.

Timing Constraints

Constraint Name	Delay (ns)	Paths	Paths Failing
TS1000	0.0	0	0
TS1001	0.0	0	0
TS1002	0.0	0	0
AUTO_TS_F2F	18.7	90	90
AUTO_TS_P2P	34.3	145	145
AUTO_TS_P2F	13.9	238	238
AUTO_TS_F2P	20.4	30	30

Constraint: TS1000

**Description: PERIOD:PERIOD_AS:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1001

**Description: PERIOD:PERIOD_C3:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1002

**Description: PERIOD:PERIOD_C1:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: AUTO_TS_F2F

**Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS**
Path	Delay (ns)	Slack (ns)
D<12>_BUFR.Q to D<12>_BUFR.D	18.700	-18.700
D<13>_BUFR.Q to D<13>_BUFR.D	18.700	-18.700
D<14>_BUFR.Q to D<14>_BUFR.D	18.700	-18.700

Constraint: AUTO_TS_P2P

**Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS**
Path	Delay (ns)	Slack (ns)
C1 to OWN	34.300	-34.300
C3 to OWN	34.300	-34.300
C1 to D<0>	26.600	-26.600

Constraint: AUTO_TS_P2F

**Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS**
Path	Delay (ns)	Slack (ns)
C1 to AUTO_CONFIG_DONE_CYCLE<0>.CLKF	13.900	-13.900
C1 to AUTO_CONFIG_DONE_CYCLE<1>.CLKF	13.900	-13.900
C1 to AUTO_CONFIG_DONE_CYCLE<2>.CLKF	13.900	-13.900

Constraint: AUTO_TS_F2P

**Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS**
Path	Delay (ns)	Slack (ns)
autoconfig.Q to OWN	20.400	-20.400
ide.Q to OWN	20.400	-20.400
autoconfig.Q to D<0>	12.700	-12.700

Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock	fEXT (MHz)	Reason
AS	71.429	Limited by Clock Pulse Width for AS
C3	53.476	Limited by Cycle Time for C3
C1	53.476	Limited by Cycle Time for C1

Setup/Hold Times for Clocks

**Setup/Hold Times for Clock C3**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
A<16>	-4.600	9.100
A<17>	-4.200	9.100
A<18>	-4.200	9.100
A<19>	-4.600	9.100
A<1>	-4.200	9.100
A<20>	-4.600	9.100
A<21>	-4.600	9.100
A<22>	-4.600	9.100
A<23>	-5.600	9.100
A<2>	-4.200	9.100
A<3>	-4.200	9.100
A<4>	-4.200	9.100
A<5>	-4.200	9.100
A<6>	-4.200	9.100
AS	-4.200	9.100
AUTOBOOT_OFF	-4.200	7.700
CFIN	-5.600	9.100
D<10>	-5.600	9.100
D<11>	-5.600	9.100
D<12>	-5.600	9.100
D<13>	-5.600	9.100
D<14>	-5.600	9.100
D<15>	-5.600	9.100
D<8>	-5.600	9.100
D<9>	-5.600	9.100
RESET	-4.200	9.100
RW	-4.200	9.100
UDS	-5.600	9.100

**Setup/Hold Times for Clock C1**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
A<16>	-4.600	9.100
A<17>	-4.200	9.100
A<18>	-4.200	9.100
A<19>	-4.600	9.100
A<1>	-4.200	9.100
A<20>	-4.600	9.100
A<21>	-4.600	9.100
A<22>	-4.600	9.100
A<23>	-5.600	9.100
A<2>	-4.200	9.100
A<3>	-4.200	9.100
A<4>	-4.200	9.100
A<5>	-4.200	9.100
A<6>	-4.200	9.100
AS	-4.200	9.100
AUTOBOOT_OFF	-4.200	7.700
CFIN	-5.600	9.100
D<10>	-5.600	9.100
D<11>	-5.600	9.100
D<12>	-5.600	9.100
D<13>	-5.600	9.100
D<14>	-5.600	9.100
D<15>	-5.600	9.100
D<8>	-5.600	9.100
D<9>	-5.600	9.100
RESET	-4.200	9.100
RW	-4.200	9.100
UDS	-5.600	9.100

Clock to Pad Timing

**Clock AS to Pad**
Destination Pad	Clock (edge) to Pad
CFOUT	17.900

**Clock C3 to Pad**
Destination Pad	Clock (edge) to Pad
OWN	34.300
D<0>	26.600
D<10>	26.600
D<11>	26.600
D<12>	26.600
D<13>	26.600
D<14>	26.600
D<15>	26.600
D<1>	26.600
D<2>	26.600
D<3>	26.600
D<4>	26.600
D<5>	26.600
D<6>	26.600
D<7>	26.600
D<8>	26.600
D<9>	26.600
SLAVE	25.600
IDE_R	17.900
IDE_W	17.900
ROM_OE	17.900

**Clock C1 to Pad**
Destination Pad	Clock (edge) to Pad
OWN	34.300
D<0>	26.600
D<10>	26.600
D<11>	26.600
D<12>	26.600
D<13>	26.600
D<14>	26.600
D<15>	26.600
D<1>	26.600
D<2>	26.600
D<3>	26.600
D<4>	26.600
D<5>	26.600
D<6>	26.600
D<7>	26.600
D<8>	26.600
D<9>	26.600
SLAVE	25.600
IDE_R	17.900
IDE_W	17.900
ROM_OE	17.900

Clock to Setup Times for Clocks

**Clock to Setup for clock C3**
Source	Destination	Delay
D<12>_BUFR.Q	D<12>_BUFR.D	18.700
D<13>_BUFR.Q	D<13>_BUFR.D	18.700
D<14>_BUFR.Q	D<14>_BUFR.D	18.700
D<15>_BUFR.Q	D<15>_BUFR.D	18.700
IDE_BASEADR<1>.Q	ide.D	11.400
IDE_BASEADR<2>.Q	ide.D	11.400
autoconfig.Q	D<12>_BUFR.D	11.400
autoconfig.Q	D<13>_BUFR.D	11.400
autoconfig.Q	D<14>_BUFR.D	11.400
IDE_BASEADR<0>.Q	ide.D	11.000
IDE_BASEADR<3>.Q	ide.D	11.000
IDE_BASEADR<4>.Q	ide.D	11.000
IDE_BASEADR<5>.Q	ide.D	11.000
IDE_BASEADR<6>.Q	ide.D	11.000
autoconfig.Q	D<15>_BUFR.D	11.000
AUTO_CONFIG_DONE_CYCLE<0>.Q	AUTO_CONFIG_DONE_CYCLE<0>.D	10.000
AUTO_CONFIG_DONE_CYCLE<1>.Q	AUTO_CONFIG_DONE_CYCLE<1>.D	10.000
AUTO_CONFIG_DONE_CYCLE<2>.Q	AUTO_CONFIG_DONE_CYCLE<2>.D	10.000
IDE_BASEADR<0>.Q	IDE_BASEADR<0>.D	10.000
IDE_BASEADR<1>.Q	IDE_BASEADR<1>.D	10.000
IDE_BASEADR<2>.Q	IDE_BASEADR<2>.D	10.000
IDE_BASEADR<3>.Q	IDE_BASEADR<3>.D	10.000
IDE_BASEADR<4>.Q	IDE_BASEADR<4>.D	10.000
IDE_BASEADR<5>.Q	IDE_BASEADR<5>.D	10.000
IDE_BASEADR<6>.Q	IDE_BASEADR<6>.D	10.000
IDE_BASEADR<7>.Q	IDE_BASEADR<7>.D	10.000
IDE_BASEADR<7>.Q	ide.D	10.000
IDE_ENABLE.Q	IDE_ENABLE.D	10.000
IDE_ENABLE.Q	IDE_R.D	10.000
IDE_ENABLE.Q	ROM_OE.D	10.000
SHUT_UP<1>.Q	SHUT_UP<1>.D	10.000
SHUT_UP<1>.Q	ide.D	10.000
autoconfig.Q	AUTO_CONFIG_DONE_CYCLE<0>.D	10.000
autoconfig.Q	AUTO_CONFIG_DONE_CYCLE<1>.D	10.000
autoconfig.Q	AUTO_CONFIG_DONE_CYCLE<2>.D	10.000
autoconfig.Q	IDE_BASEADR<0>.D	10.000
autoconfig.Q	IDE_BASEADR<1>.D	10.000
autoconfig.Q	IDE_BASEADR<2>.D	10.000
autoconfig.Q	IDE_BASEADR<3>.D	10.000
autoconfig.Q	IDE_BASEADR<4>.D	10.000
autoconfig.Q	IDE_BASEADR<5>.D	10.000
autoconfig.Q	IDE_BASEADR<6>.D	10.000
autoconfig.Q	IDE_BASEADR<7>.D	10.000
autoconfig.Q	SHUT_UP<1>.D	10.000
ide.Q	IDE_ENABLE.D	10.000
ide.Q	IDE_R.D	10.000
ide.Q	IDE_W.D	10.000
ide.Q	ROM_OE.D	10.000

**Clock to Setup for clock C1**
Source	Destination	Delay
D<12>_BUFR.Q	D<12>_BUFR.D	18.700
D<13>_BUFR.Q	D<13>_BUFR.D	18.700
D<14>_BUFR.Q	D<14>_BUFR.D	18.700
D<15>_BUFR.Q	D<15>_BUFR.D	18.700
IDE_BASEADR<1>.Q	ide.D	11.400
IDE_BASEADR<2>.Q	ide.D	11.400
autoconfig.Q	D<12>_BUFR.D	11.400
autoconfig.Q	D<13>_BUFR.D	11.400
autoconfig.Q	D<14>_BUFR.D	11.400
IDE_BASEADR<0>.Q	ide.D	11.000
IDE_BASEADR<3>.Q	ide.D	11.000
IDE_BASEADR<4>.Q	ide.D	11.000
IDE_BASEADR<5>.Q	ide.D	11.000
IDE_BASEADR<6>.Q	ide.D	11.000
autoconfig.Q	D<15>_BUFR.D	11.000
AUTO_CONFIG_DONE_CYCLE<0>.Q	AUTO_CONFIG_DONE_CYCLE<0>.D	10.000
AUTO_CONFIG_DONE_CYCLE<1>.Q	AUTO_CONFIG_DONE_CYCLE<1>.D	10.000
AUTO_CONFIG_DONE_CYCLE<2>.Q	AUTO_CONFIG_DONE_CYCLE<2>.D	10.000
IDE_BASEADR<0>.Q	IDE_BASEADR<0>.D	10.000
IDE_BASEADR<1>.Q	IDE_BASEADR<1>.D	10.000
IDE_BASEADR<2>.Q	IDE_BASEADR<2>.D	10.000
IDE_BASEADR<3>.Q	IDE_BASEADR<3>.D	10.000
IDE_BASEADR<4>.Q	IDE_BASEADR<4>.D	10.000
IDE_BASEADR<5>.Q	IDE_BASEADR<5>.D	10.000
IDE_BASEADR<6>.Q	IDE_BASEADR<6>.D	10.000
IDE_BASEADR<7>.Q	IDE_BASEADR<7>.D	10.000
IDE_BASEADR<7>.Q	ide.D	10.000
IDE_ENABLE.Q	IDE_ENABLE.D	10.000
IDE_ENABLE.Q	IDE_R.D	10.000
IDE_ENABLE.Q	ROM_OE.D	10.000
SHUT_UP<1>.Q	SHUT_UP<1>.D	10.000
SHUT_UP<1>.Q	ide.D	10.000
autoconfig.Q	AUTO_CONFIG_DONE_CYCLE<0>.D	10.000
autoconfig.Q	AUTO_CONFIG_DONE_CYCLE<1>.D	10.000
autoconfig.Q	AUTO_CONFIG_DONE_CYCLE<2>.D	10.000
autoconfig.Q	IDE_BASEADR<0>.D	10.000
autoconfig.Q	IDE_BASEADR<1>.D	10.000
autoconfig.Q	IDE_BASEADR<2>.D	10.000
autoconfig.Q	IDE_BASEADR<3>.D	10.000
autoconfig.Q	IDE_BASEADR<4>.D	10.000
autoconfig.Q	IDE_BASEADR<5>.D	10.000
autoconfig.Q	IDE_BASEADR<6>.D	10.000
autoconfig.Q	IDE_BASEADR<7>.D	10.000
autoconfig.Q	SHUT_UP<1>.D	10.000
ide.Q	IDE_ENABLE.D	10.000
ide.Q	IDE_R.D	10.000
ide.Q	IDE_W.D	10.000
ide.Q	ROM_OE.D	10.000

Pad to Pad List

Source Pad	Destination Pad	Delay
AS	OWN	18.700
AS	D<0>	11.000
AS	D<10>	11.000
AS	D<11>	11.000
AS	D<12>	11.000
AS	D<13>	11.000
AS	D<14>	11.000
AS	D<15>	11.000
AS	D<1>	11.000
AS	D<2>	11.000
AS	D<3>	11.000
AS	D<4>	11.000
AS	D<5>	11.000
AS	D<6>	11.000
AS	D<7>	11.000
AS	D<8>	11.000
AS	D<9>	11.000
AS	DQ<0>	11.000
AS	DQ<10>	11.000
AS	DQ<11>	11.000
AS	DQ<12>	11.000
AS	DQ<13>	11.000
AS	DQ<14>	11.000
AS	DQ<15>	11.000
AS	DQ<1>	11.000
AS	DQ<2>	11.000
AS	DQ<3>	11.000
AS	DQ<4>	11.000
AS	DQ<5>	11.000
AS	DQ<6>	11.000
AS	DQ<7>	11.000
AS	DQ<8>	11.000
AS	DQ<9>	11.000
CP_IRQ	INT_OUT	11.000
RW	D<0>	11.000
RW	D<10>	11.000
RW	D<11>	11.000
RW	D<12>	11.000
RW	D<13>	11.000
RW	D<14>	11.000
RW	D<15>	11.000
RW	D<1>	11.000
RW	D<2>	11.000
RW	D<3>	11.000
RW	D<4>	11.000
RW	D<5>	11.000
RW	D<6>	11.000
RW	D<7>	11.000
RW	D<8>	11.000
RW	D<9>	11.000
RW	DQ<0>	11.000
RW	DQ<10>	11.000
RW	DQ<11>	11.000
RW	DQ<12>	11.000
RW	DQ<13>	11.000
RW	DQ<14>	11.000
RW	DQ<15>	11.000
RW	DQ<1>	11.000
RW	DQ<2>	11.000
RW	DQ<3>	11.000
RW	DQ<4>	11.000
RW	DQ<5>	11.000
RW	DQ<6>	11.000
RW	DQ<7>	11.000
RW	DQ<8>	11.000
RW	DQ<9>	11.000
A<10>	A_LAN<9>	10.000
A<10>	IDE_A<1>	10.000
A<11>	A_LAN<10>	10.000
A<11>	IDE_A<2>	10.000
A<12>	A_LAN<11>	10.000
A<12>	IDE_CS<0>	10.000
A<13>	A_LAN<12>	10.000
A<13>	IDE_CS<1>	10.000
A<14>	A_LAN<13>	10.000
A<1>	A_LAN<0>	10.000
A<2>	A_LAN<1>	10.000
A<3>	A_LAN<2>	10.000
A<4>	A_LAN<3>	10.000
A<5>	A_LAN<4>	10.000
A<6>	A_LAN<5>	10.000
A<7>	A_LAN<6>	10.000
A<8>	A_LAN<7>	10.000
A<9>	A_LAN<8>	10.000
A<9>	IDE_A<0>	10.000
AS	SLAVE	10.000
D<0>	DQ<0>	10.000
D<10>	DQ<10>	10.000
D<11>	DQ<11>	10.000
D<12>	DQ<12>	10.000
D<13>	DQ<13>	10.000
D<14>	DQ<14>	10.000
D<15>	DQ<15>	10.000
D<1>	DQ<1>	10.000
D<2>	DQ<2>	10.000
D<3>	DQ<3>	10.000
D<4>	DQ<4>	10.000
D<5>	DQ<5>	10.000
D<6>	DQ<6>	10.000
D<7>	DQ<7>	10.000
D<8>	DQ<8>	10.000
D<9>	DQ<9>	10.000

Number of paths analyzed: 503
Number of Timing errors: 503
Analysis Completed: Wed Dec 28 23:10:11 2016