cpldfit:  version P.68d                             Xilinx Inc.
                                  Fitter Report
Design Name: LAN_IDE_CP                          Date:  1-15-2017,  0:06AM
Device Used: XC95288XL-10-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
125/288 ( 43%) 515 /1440 ( 36%) 387/864 ( 45%)   49 /288 ( 17%) 106/117 ( 91%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          17/18       26/54       53/90       8/ 8*
FB2          10/18       14/54       28/90      10/10*
FB3           6/18       26/54       25/90       3/ 5
FB4          14/18       26/54       70/90       6/ 6*
FB5           7/18       32/54       48/90       7/ 8
FB6           8/18       25/54       25/90       8/ 8*
FB7           5/18       26/54       66/90       4/ 4*
FB8           6/18       26/54       27/90       5/ 5*
FB9           4/18       25/54       24/90       9/ 9*
FB10         15/18       20/54       31/90      10/10*
FB11          7/18       26/54       25/90       7/ 7*
FB12          9/18       26/54       32/90       5/ 6
FB13          5/18       25/54       20/90       3/ 6
FB14          7/18       26/54       18/90       7/ 8
FB15          4/18       25/54       19/90       8/ 9
FB16          1/18       13/54        4/90       6/ 8
             -----       -----       -----      -----    
            125/288     387/864     515/1440   106/117

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   33          33    |  I/O              :   100     109
Output        :   41          41    |  GCK/IO           :     1       3
Bidirectional :   32          32    |  GTS/IO           :     4       4
GCK           :    0           0    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total    106         106

** Power Data **

There are 125 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'LAN_IDE_CP.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
   constraint 'P30'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
WARNING:Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will
   be deleted.
WARNING:Cpld:1007 - Removing unused input(s) 'A<15>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'CLK_EXT'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'CP_IRQ'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'DS0'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'DS1'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'FCS'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'LAN_INT'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'Z3'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
*************************  Summary of Mapped Logic  ************************

** 73 Outputs **

Signal                      Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                        Pts   Inps          No.  Type    Use     Mode Rate State
D<5>                        5     7     FB1_5   20   I/O     I/O     STD  FAST 
D<4>                        5     7     FB1_6   21   I/O     I/O     STD  FAST 
IDE_CS<0>                   1     1     FB1_8   22   I/O     O       STD  FAST 
IDE_CS<1>                   1     1     FB1_10  23   I/O     O       STD  FAST 
IDE_A<0>                    1     1     FB1_12  24   I/O     O       STD  FAST 
IDE_A<2>                    1     1     FB1_14  25   I/O     O       STD  FAST 
IDE_A<1>                    1     1     FB1_15  26   I/O     O       STD  FAST 
IDE_R                       1     2     FB1_17  27   I/O     O       STD  FAST 
A_LAN<4>                    1     1     FB2_2   9    I/O     O       STD  FAST 
A_LAN<7>                    1     1     FB2_3   10   I/O     O       STD  FAST 
A_LAN<6>                    1     1     FB2_5   11   I/O     O       STD  FAST 
LAN_CFG<1>                  0     0     FB2_6   12   I/O     O       STD  FAST 
LAN_CFG<3>                  0     0     FB2_8   13   I/O     O       STD  FAST 
D<6>                        5     7     FB2_10  14   I/O     I/O     STD  FAST 
D<3>                        5     7     FB2_12  15   I/O     I/O     STD  FAST 
D<7>                        5     7     FB2_14  16   I/O     I/O     STD  FAST 
D<1>                        5     7     FB2_15  17   I/O     I/O     STD  FAST 
D<8>                        5     7     FB2_17  19   I/O     I/O     STD  FAST 
IDE_W                       1     2     FB3_2   28   I/O     O       STD  FAST 
INT_OUT                     0     0     FB3_14  32   GCK/I/O O       STD  FAST 
D<0>                        5     7     FB4_2   2    GTS/I/O I/O     STD  FAST 
A_LAN<1>                    1     1     FB4_5   3    GTS/I/O O       STD  FAST 
A_LAN<0>                    1     1     FB4_6   4    I/O     O       STD  FAST 
A_LAN<3>                    1     1     FB4_8   5    GTS/I/O O       STD  FAST 
A_LAN<2>                    1     1     FB4_12  6    GTS/I/O O       STD  FAST 
A_LAN<5>                    1     1     FB4_14  7    I/O     O       STD  FAST 
CP_CS                       19    19    FB5_2   34   I/O     O       STD  FAST SET
ROM_OE                      1     2     FB5_5   35   I/O     O       STD  FAST 
D<2>                        5     7     FB5_10  39   I/O     I/O     STD  FAST 
D<9>                        5     7     FB5_12  40   I/O     I/O     STD  FAST 
D<10>                       5     7     FB5_14  41   I/O     I/O     STD  FAST 
D<11>                       5     7     FB5_15  43   I/O     I/O     STD  FAST 
D<12>                       8     8     FB5_17  44   I/O     I/O     STD  FAST 
LAN_CFG<2>                  0     0     FB6_2   135  I/O     O       STD  FAST 
A_LAN<13>                   1     1     FB6_3   136  I/O     O       STD  FAST 
A_LAN<12>                   1     1     FB6_5   137  I/O     O       STD  FAST 
A_LAN<10>                   1     1     FB6_6   138  I/O     O       STD  FAST 
A_LAN<11>                   1     1     FB6_8   139  I/O     O       STD  FAST 
A_LAN<8>                    1     1     FB6_10  140  I/O     O       STD  FAST 
A_LAN<9>                    1     1     FB6_14  142  I/O     O       STD  FAST 

Signal                      Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                        Pts   Inps          No.  Type    Use     Mode Rate State
D<13>                       8     8     FB7_3   45   I/O     I/O     STD  FAST 
D<14>                       8     8     FB7_5   46   I/O     I/O     STD  FAST 
D<15>                       8     8     FB7_12  48   I/O     I/O     STD  FAST 
DQ<12>                      2     2     FB8_2   130  I/O     I/O     STD  FAST 
DQ<14>                      2     2     FB8_3   131  I/O     I/O     STD  FAST 
LAN_WRH                     1     2     FB8_5   132  I/O     O       STD  FAST 
LAN_CS                      19    19    FB8_8   133  I/O     O       STD  FAST RESET
LAN_RD                      1     2     FB8_10  134  I/O     O       STD  FAST 
DQ<1>                       2     2     FB10_2  117  I/O     I/O     STD  FAST 
DQ<0>                       2     2     FB10_3  118  I/O     I/O     STD  FAST 
DQ<3>                       2     2     FB10_5  119  I/O     I/O     STD  FAST 
DQ<2>                       2     2     FB10_6  120  I/O     I/O     STD  FAST 
DQ<5>                       2     2     FB10_8  121  I/O     I/O     STD  FAST 
DQ<4>                       2     2     FB10_10 124  I/O     I/O     STD  FAST 
DQ<7>                       2     2     FB10_11 125  I/O     I/O     STD  FAST 
DQ<6>                       2     2     FB10_12 126  I/O     I/O     STD  FAST 
DQ<8>                       2     2     FB10_14 128  I/O     I/O     STD  FAST 
DQ<10>                      2     2     FB10_17 129  I/O     I/O     STD  FAST 
ROM_B<0>                    0     0     FB11_12 68   I/O     O       STD  FAST 
ROM_B<1>                    0     0     FB11_14 69   I/O     O       STD  FAST 
CP_WE                       1     2     FB11_17 70   I/O     O       STD  FAST 
LAN_CFG<4>                  0     0     FB12_2  110  I/O     O       STD  FAST 
DQ<15>                      2     2     FB12_5  112  I/O     I/O     STD  FAST 
DQ<13>                      2     2     FB12_8  113  I/O     I/O     STD  FAST 
DQ<11>                      2     2     FB12_10 115  I/O     I/O     STD  FAST 
DQ<9>                       2     2     FB12_12 116  I/O     I/O     STD  FAST 
CP_RD                       1     2     FB13_2  71   I/O     O       STD  FAST 
LAN_WRL                     1     2     FB13_14 76   I/O     O       STD  FAST 
OVR                         1     2     FB14_3  100  I/O     O       STD  FAST 
CFOUT                       1     2     FB14_11 105  I/O     O       STD  FAST 
SLAVE                       2     5     FB14_14 106  I/O     O       STD  FAST 
OWN                         1     1     FB14_15 107  I/O     O       STD  FAST 
DTACK                       1     3     FB15_12 85   I/O     O       STD  FAST 

** 52 Buried Nodes **

Signal                      Total Total Loc     Pwr  Reg Init
Name                        Pts   Inps          Mode State
LAN_WRL_S                   2     4     FB1_2   STD  RESET
LAN_WRH_S                   2     4     FB1_3   STD  RESET
DS_D                        2     3     FB1_4   STD  RESET
LAN_RD_S                    3     5     FB1_7   STD  RESET
CP_WE_S                     3     6     FB1_9   STD  RESET
CP_RD_S                     3     6     FB1_11  STD  RESET
$OpTx$FX_DC$176__$INT       3     5     FB1_13  STD  
$OpTx$FX_DC$175__$INT       3     6     FB1_16  STD  
Dout1<3>                    16    14    FB1_18  STD  RESET
IDE_BASEADR<3>              6     19    FB3_1   STD  RESET
IDE_BASEADR<2>              6     19    FB3_16  STD  RESET
IDE_BASEADR<1>              6     19    FB3_17  STD  RESET
IDE_BASEADR<0>              6     19    FB3_18  STD  RESET
AUTO_CONFIG_DONE_CYCLE<0>   10    20    FB4_3   STD  RESET
SHUT_UP<0>                  4     17    FB4_4   STD  RESET
AUTO_CONFIG_DONE_CYCLE<1>   10    21    FB4_7   STD  RESET
SHUT_UP<1>                  4     17    FB4_9   STD  RESET
SHUT_UP<2>                  4     17    FB4_10  STD  RESET
AUTO_CONFIG_DONE<0>         3     5     FB4_11  STD  RESET
AUTO_CONFIG_DONE<1>         3     5     FB4_13  STD  RESET
Dout1<1>                    22    15    FB4_16  STD  RESET
ide                         19    19    FB6_17  STD  RESET
Dout1<2>                    20    15    FB7_8   STD  RESET
Dout1<0>                    22    16    FB7_15  STD  RESET
SHUT_UP<2>/SHUT_UP<2>_CLKF  2     2     FB8_18  STD  
LAN_BASEADR<6>              6     19    FB9_1   STD  RESET
LAN_BASEADR<4>              6     19    FB9_16  STD  RESET
LAN_BASEADR<2>              6     19    FB9_17  STD  RESET
LAN_BASEADR<0>              6     19    FB9_18  STD  RESET
SLAVE_OBUF__$INT            2     5     FB10_9  STD  
ROM_OE_S                    2     6     FB10_13 STD  RESET
IDE_W_S                     2     5     FB10_15 STD  RESET
IDE_R_S                     2     6     FB10_16 STD  RESET
IDE_ENABLE                  3     6     FB10_18 STD  RESET
IDE_BASEADR<7>              6     19    FB11_13 STD  RESET
IDE_BASEADR<6>              6     19    FB11_15 STD  RESET
IDE_BASEADR<5>              6     19    FB11_16 STD  RESET
IDE_BASEADR<4>              6     19    FB11_18 STD  RESET
LAN_BASEADR<7>              6     19    FB12_1  STD  RESET
LAN_BASEADR<5>              6     19    FB12_16 STD  RESET

Signal                      Total Total Loc     Pwr  Reg Init
Name                        Pts   Inps          Mode State
LAN_BASEADR<3>              6     19    FB12_17 STD  RESET
LAN_BASEADR<1>              6     19    FB12_18 STD  RESET
CP_BASEADR<4>               6     19    FB13_16 STD  RESET
CP_BASEADR<3>               6     19    FB13_17 STD  RESET
CP_BASEADR<2>               6     19    FB13_18 STD  RESET
ide/ide_RSTF__$INT          1     2     FB14_16 STD  
CP_BASEADR<1>               6     19    FB14_17 STD  RESET
CP_BASEADR<0>               6     19    FB14_18 STD  RESET
CP_BASEADR<7>               6     19    FB15_16 STD  RESET
CP_BASEADR<6>               6     19    FB15_17 STD  RESET
CP_BASEADR<5>               6     19    FB15_18 STD  RESET
autoconfig                  4     13    FB16_18 STD  RESET

** 33 Inputs **

Signal                      Loc     Pin  Pin     Pin     
Name                                No.  Type    Use     
IDE_WAIT                    FB3_15  33   I/O     I
RESET                       FB6_15  143  GSR/I/O I
A<5>                        FB7_15  49   I/O     I
A<4>                        FB9_2   50   I/O     I
A<6>                        FB9_3   51   I/O     I
A<3>                        FB9_5   52   I/O     I
A<7>                        FB9_6   53   I/O     I
A<2>                        FB9_8   54   I/O     I
A<8>                        FB9_11  56   I/O     I
A<1>                        FB9_12  57   I/O     I
A<9>                        FB9_14  58   I/O     I
A<10>                       FB9_17  59   I/O     I
A<11>                       FB11_3  60   I/O     I
A<12>                       FB11_5  61   I/O     I
A<13>                       FB11_10 64   I/O     I
A<14>                       FB11_11 66   I/O     I
AUTOBOOT_OFF                FB13_11 75   I/O     I
C3                          FB14_6  102  I/O     I
C1                          FB14_8  103  I/O     I
CFIN                        FB14_10 104  I/O     I
AS                          FB15_3  80   I/O     I
UDS                         FB15_8  81   I/O     I
LDS                         FB15_10 82   I/O     I
RW                          FB15_11 83   I/O     I
A<23>                       FB15_14 86   I/O     I
A<22>                       FB15_15 87   I/O     I
A<21>                       FB15_17 88   I/O     I
A<20>                       FB16_2  91   I/O     I
A<19>                       FB16_3  92   I/O     I
A<18>                       FB16_6  94   I/O     I
A<17>                       FB16_8  95   I/O     I
A<16>                       FB16_11 97   I/O     I
BERR                        FB16_12 98   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               26/28
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\5   0     FB1_1         (b)     (b)
LAN_WRL_S             2       0   /\1   2     FB1_2         (b)     (b)
LAN_WRH_S             2       0     0   3     FB1_3         (b)     (b)
DS_D                  2       0     0   3     FB1_4         (b)     (b)
D<5>                  5       0     0   0     FB1_5   20    I/O     I/O
D<4>                  5       0     0   0     FB1_6   21    I/O     I/O
LAN_RD_S              3       0     0   2     FB1_7         (b)     (b)
IDE_CS<0>             1       0     0   4     FB1_8   22    I/O     O
CP_WE_S               3       0     0   2     FB1_9         (b)     (b)
IDE_CS<1>             1       0     0   4     FB1_10  23    I/O     O
CP_RD_S               3       0     0   2     FB1_11        (b)     (b)
IDE_A<0>              1       0     0   4     FB1_12  24    I/O     O
$OpTx$FX_DC$176__$INT
                      3       0     0   2     FB1_13        (b)     (b)
IDE_A<2>              1       0     0   4     FB1_14  25    I/O     O
IDE_A<1>              1       0     0   4     FB1_15  26    I/O     O
$OpTx$FX_DC$175__$INT
                      3       0   \/1   1     FB1_16        (b)     (b)
IDE_R                 1       1<- \/5   0     FB1_17  27    I/O     O
Dout1<3>             16      11<-   0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$175__$INT  10: A<4>              19: LDS 
  2: AS                     11: A<5>              20: DQ<5>.PIN 
  3: AUTO_CONFIG_DONE<1>    12: A<6>              21: DQ<4>.PIN 
  4: A<1>                   13: A<9>              22: RESET 
  5: A<11>                  14: A<10>             23: RW 
  6: A<12>                  15: CP_CS             24: SHUT_UP<2>/SHUT_UP<2>_CLKF 
  7: A<13>                  16: Dout1<3>          25: UDS 
  8: A<2>                   17: IDE_R_S           26: autoconfig 
  9: A<3>                   18: LAN_CS           

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
LAN_WRL_S            .................XX...XX................ 4
LAN_WRH_S            .................X....XXX............... 4
DS_D                 ..................X....XX............... 3
D<5>                 X.............X..XXX..X.X............... 7
D<4>                 X.............X..XX.X.X.X............... 7
LAN_RD_S             .................XX...XXX............... 5
IDE_CS<0>            .....X.................................. 1
CP_WE_S              ..............X...X..XXXX............... 6
IDE_CS<1>            ......X................................. 1
CP_RD_S              ..............X...X..XXXX............... 6
IDE_A<0>             ............X........................... 1
$OpTx$FX_DC$176__$INT 
                     ..............X..XX...X.X............... 5
IDE_A<2>             ....X................................... 1
IDE_A<1>             .............X.......................... 1
$OpTx$FX_DC$175__$INT 
                     ..............X..XX...X.XX.............. 6
IDE_R                .X..............X....................... 2
Dout1<3>             .XXX...XXXXX...X..X..X.XXX.............. 14
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               14/40
Number of signals used by logic mapping into function block:  14
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
A_LAN<4>              1       0     0   4     FB2_2   9     I/O     O
A_LAN<7>              1       0     0   4     FB2_3   10    I/O     O
(unused)              0       0     0   5     FB2_4         (b)     
A_LAN<6>              1       0     0   4     FB2_5   11    I/O     O
LAN_CFG<1>            0       0     0   5     FB2_6   12    I/O     O
(unused)              0       0     0   5     FB2_7         (b)     
LAN_CFG<3>            0       0     0   5     FB2_8   13    I/O     O
(unused)              0       0     0   5     FB2_9         (b)     
D<6>                  5       0     0   0     FB2_10  14    I/O     I/O
(unused)              0       0     0   5     FB2_11        (b)     
D<3>                  5       0     0   0     FB2_12  15    I/O     I/O
(unused)              0       0     0   5     FB2_13        (b)     
D<7>                  5       0     0   0     FB2_14  16    I/O     I/O
D<1>                  5       0     0   0     FB2_15  17    I/O     I/O
(unused)              0       0     0   5     FB2_16        (b)     
D<8>                  5       0     0   0     FB2_17  19    I/O     I/O
(unused)              0       0     0   5     FB2_18        (b)     

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$175__$INT   6: LAN_CS            11: DQ<3>.PIN 
  2: A<5>                    7: LDS               12: DQ<1>.PIN 
  3: A<7>                    8: DQ<8>.PIN         13: RW 
  4: A<8>                    9: DQ<7>.PIN         14: UDS 
  5: CP_CS                  10: DQ<6>.PIN        

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
A_LAN<4>             .X...................................... 1
A_LAN<7>             ...X.................................... 1
A_LAN<6>             ..X..................................... 1
LAN_CFG<1>           ........................................ 0
LAN_CFG<3>           ........................................ 0
D<6>                 X...XXX..X..XX.......................... 7
D<3>                 X...XXX...X.XX.......................... 7
D<7>                 X...XXX.X...XX.......................... 7
D<1>                 X...XXX....XXX.......................... 7
D<8>                 X...XXXX....XX.......................... 7
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               26/28
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
IDE_BASEADR<3>        6       2<- /\1   0     FB3_1         (b)     (b)
IDE_W                 1       0   /\2   2     FB3_2   28    I/O     O
(unused)              0       0     0   5     FB3_3         (b)     
(unused)              0       0     0   5     FB3_4         (b)     
(unused)              0       0     0   5     FB3_5         (b)     
(unused)              0       0     0   5     FB3_6         (b)     
(unused)              0       0     0   5     FB3_7         (b)     
(unused)              0       0     0   5     FB3_8         (b)     
(unused)              0       0     0   5     FB3_9         (b)     
(unused)              0       0     0   5     FB3_10  30    GCK/I/O 
(unused)              0       0     0   5     FB3_11        (b)     
(unused)              0       0     0   5     FB3_12  31    I/O     
(unused)              0       0     0   5     FB3_13        (b)     
INT_OUT               0       0     0   5     FB3_14  32    GCK/I/O O
(unused)              0       0   \/2   3     FB3_15  33    I/O     I
IDE_BASEADR<2>        6       2<- \/1   0     FB3_16        (b)     (b)
IDE_BASEADR<1>        6       1<-   0   0     FB3_17        (b)     (b)
IDE_BASEADR<0>        6       1<-   0   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: AS                   10: D<10>.PIN         19: IDE_W_S 
  2: AUTO_CONFIG_DONE<0>  11: D<11>.PIN         20: LDS 
  3: AUTO_CONFIG_DONE<1>  12: D<8>.PIN          21: RESET 
  4: A<1>                 13: D<9>.PIN          22: RW 
  5: A<2>                 14: DS_D              23: SHUT_UP<2> 
  6: A<3>                 15: IDE_BASEADR<0>    24: SHUT_UP<2>/SHUT_UP<2>_CLKF 
  7: A<4>                 16: IDE_BASEADR<1>    25: UDS 
  8: A<5>                 17: IDE_BASEADR<2>    26: autoconfig 
  9: A<6>                 18: IDE_BASEADR<3>   

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
IDE_BASEADR<3>       XXXXXXXXX.X..X...X.XXXXXXX.............. 19
IDE_W                X.................X..................... 2
INT_OUT              ........................................ 0
IDE_BASEADR<2>       XXXXXXXXXX...X..X..XXXXXXX.............. 19
IDE_BASEADR<1>       XXXXXXXXX...XX.X...XXXXXXX.............. 19
IDE_BASEADR<0>       XXXXXXXXX..X.XX....XXXXXXX.............. 19
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               26/28
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/3   2     FB4_1         (b)     (b)
D<0>                  5       3<- \/3   0     FB4_2   2     GTS/I/O I/O
AUTO_CONFIG_DONE_CYCLE<0>
                     10       5<-   0   0     FB4_3         (b)     (b)
SHUT_UP<0>            4       1<- /\2   0     FB4_4         (b)     (b)
A_LAN<1>              1       0   /\1   3     FB4_5   3     GTS/I/O O
A_LAN<0>              1       0   \/3   1     FB4_6   4     I/O     O
AUTO_CONFIG_DONE_CYCLE<1>
                     10       5<-   0   0     FB4_7         (b)     (b)
A_LAN<3>              1       0   /\2   2     FB4_8   5     GTS/I/O O
SHUT_UP<1>            4       0     0   1     FB4_9         (b)     (b)
SHUT_UP<2>            4       0     0   1     FB4_10        (b)     (b)
AUTO_CONFIG_DONE<0>   3       0     0   2     FB4_11        (b)     (b)
A_LAN<2>              1       0     0   4     FB4_12  6     GTS/I/O O
AUTO_CONFIG_DONE<1>   3       0     0   2     FB4_13        (b)     (b)
A_LAN<5>              1       0   \/4   0     FB4_14  7     I/O     O
(unused)              0       0   \/5   0     FB4_15        (b)     (b)
Dout1<1>             22      17<-   0   0     FB4_16        (b)     (b)
(unused)              0       0   /\5   0     FB4_17        (b)     (b)
(unused)              0       0   /\3   2     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$175__$INT      10: A<4>              19: RESET 
  2: AS                         11: A<5>              20: RW 
  3: AUTO_CONFIG_DONE<0>        12: A<6>              21: SHUT_UP<0> 
  4: AUTO_CONFIG_DONE<1>        13: CP_CS             22: SHUT_UP<1> 
  5: AUTO_CONFIG_DONE_CYCLE<0>  14: DS_D              23: SHUT_UP<2> 
  6: AUTO_CONFIG_DONE_CYCLE<1>  15: Dout1<1>          24: SHUT_UP<2>/SHUT_UP<2>_CLKF 
  7: A<1>                       16: LAN_CS            25: UDS 
  8: A<2>                       17: LDS               26: autoconfig 
  9: A<3>                       18: DQ<0>.PIN        

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
D<0>                 X...........X..XXX.X....X............... 7
AUTO_CONFIG_DONE_CYCLE<0> 
                     .XXXX.XXXXXX.X..X.XXXXXXXX.............. 20
SHUT_UP<0>           .XXX..XXXXXX.X..X.XXX..XXX.............. 17
A_LAN<1>             .......X................................ 1
A_LAN<0>             ......X................................. 1
AUTO_CONFIG_DONE_CYCLE<1> 
                     .XXXXXXXXXXX.X..X.XXXXXXXX.............. 21
A_LAN<3>             .........X.............................. 1
SHUT_UP<1>           .XXX..XXXXXX.X..X.XX.X.XXX.............. 17
SHUT_UP<2>           .XXX..XXXXXX.X..X.XX..XXXX.............. 17
AUTO_CONFIG_DONE<0>  .XX.X.............X....X................ 5
A_LAN<2>             ........X............................... 1
AUTO_CONFIG_DONE<1>  .X.X.X............X....X................ 5
A_LAN<5>             ...........X............................ 1
Dout1<1>             .XXX..XXXXXX..X.X.X....XXX.............. 15
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               32/22
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/5   0     FB5_1         (b)     (b)
CP_CS                19      14<-   0   0     FB5_2   34    I/O     O
(unused)              0       0   /\5   0     FB5_3         (b)     (b)
(unused)              0       0   /\4   1     FB5_4         (b)     (b)
ROM_OE                1       0     0   4     FB5_5   35    I/O     O
(unused)              0       0     0   5     FB5_6         (b)     
(unused)              0       0     0   5     FB5_7         (b)     
(unused)              0       0     0   5     FB5_8   38    GCK/I/O 
(unused)              0       0     0   5     FB5_9         (b)     
D<2>                  5       0     0   0     FB5_10  39    I/O     I/O
(unused)              0       0     0   5     FB5_11        (b)     
D<9>                  5       0     0   0     FB5_12  40    I/O     I/O
(unused)              0       0     0   5     FB5_13        (b)     
D<10>                 5       0     0   0     FB5_14  41    I/O     I/O
D<11>                 5       0     0   0     FB5_15  43    I/O     I/O
(unused)              0       0   \/2   3     FB5_16        (b)     (b)
D<12>                 8       3<-   0   0     FB5_17  44    I/O     I/O
(unused)              0       0   /\1   4     FB5_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$175__$INT  12: CP_BASEADR<1>     23: DQ<12>.PIN 
  2: AS                     13: CP_BASEADR<2>     24: DQ<11>.PIN 
  3: A<16>                  14: CP_BASEADR<3>     25: DQ<10>.PIN 
  4: A<17>                  15: CP_BASEADR<4>     26: DQ<9>.PIN 
  5: A<18>                  16: CP_BASEADR<5>     27: DQ<2>.PIN 
  6: A<19>                  17: CP_BASEADR<6>     28: ROM_OE_S 
  7: A<20>                  18: CP_BASEADR<7>     29: RW 
  8: A<21>                  19: CP_CS             30: SHUT_UP<1> 
  9: A<22>                  20: Dout1<0>          31: UDS 
 10: A<23>                  21: LAN_CS            32: ide/ide_RSTF__$INT 
 11: CP_BASEADR<0>          22: LDS              

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
CP_CS                .XXXXXXXXXXXXXXXXX...........X.X........ 19
ROM_OE               .X.........................X............ 2
D<2>                 X.................X.XX....X.X.X......... 7
D<9>                 X.................X.XX...X..X.X......... 7
D<10>                X.................X.XX..X...X.X......... 7
D<11>                X.................X.XX.X....X.X......... 7
D<12>                X.................XXXXX.....X.X......... 8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               25/29
Number of signals used by logic mapping into function block:  25
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB6_1         (b)     
LAN_CFG<2>            0       0     0   5     FB6_2   135   I/O     O
A_LAN<13>             1       0     0   4     FB6_3   136   I/O     O
(unused)              0       0     0   5     FB6_4         (b)     
A_LAN<12>             1       0     0   4     FB6_5   137   I/O     O
A_LAN<10>             1       0     0   4     FB6_6   138   I/O     O
(unused)              0       0     0   5     FB6_7         (b)     
A_LAN<11>             1       0     0   4     FB6_8   139   I/O     O
(unused)              0       0     0   5     FB6_9         (b)     
A_LAN<8>              1       0     0   4     FB6_10  140   I/O     O
(unused)              0       0     0   5     FB6_11        (b)     
(unused)              0       0     0   5     FB6_12        (b)     
(unused)              0       0     0   5     FB6_13        (b)     
A_LAN<9>              1       0     0   4     FB6_14  142   I/O     O
(unused)              0       0   \/4   1     FB6_15  143   GSR/I/O I
(unused)              0       0   \/5   0     FB6_16        (b)     (b)
ide                  19      14<-   0   0     FB6_17        (b)     (b)
(unused)              0       0   /\5   0     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: AS                10: A<11>             18: IDE_BASEADR<2> 
  2: A<16>             11: A<12>             19: IDE_BASEADR<3> 
  3: A<17>             12: A<13>             20: IDE_BASEADR<4> 
  4: A<18>             13: A<14>             21: IDE_BASEADR<5> 
  5: A<19>             14: A<9>              22: IDE_BASEADR<6> 
  6: A<20>             15: A<10>             23: IDE_BASEADR<7> 
  7: A<21>             16: IDE_BASEADR<0>    24: SHUT_UP<2> 
  8: A<22>             17: IDE_BASEADR<1>    25: ide/ide_RSTF__$INT 
  9: A<23>            

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
LAN_CFG<2>           ........................................ 0
A_LAN<13>            ............X........................... 1
A_LAN<12>            ...........X............................ 1
A_LAN<10>            .........X.............................. 1
A_LAN<11>            ..........X............................. 1
A_LAN<8>             .............X.......................... 1
A_LAN<9>             ..............X......................... 1
ide                  XXXXXXXXX......XXXXXXXXXX............... 19
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               26/28
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB7_1         (b)     
(unused)              0       0   \/3   2     FB7_2         (b)     (b)
D<13>                 8       3<-   0   0     FB7_3   45    I/O     I/O
(unused)              0       0   \/3   2     FB7_4         (b)     (b)
D<14>                 8       3<-   0   0     FB7_5   46    I/O     I/O
(unused)              0       0   \/5   0     FB7_6         (b)     (b)
(unused)              0       0   \/5   0     FB7_7         (b)     (b)
Dout1<2>             20      15<-   0   0     FB7_8         (b)     (b)
(unused)              0       0   /\5   0     FB7_9         (b)     (b)
(unused)              0       0     0   5     FB7_10        (b)     
(unused)              0       0   \/3   2     FB7_11        (b)     (b)
D<15>                 8       3<-   0   0     FB7_12  48    I/O     I/O
(unused)              0       0   \/5   0     FB7_13        (b)     (b)
(unused)              0       0   \/5   0     FB7_14        (b)     (b)
Dout1<0>             22      17<-   0   0     FB7_15  49    I/O     I
(unused)              0       0   /\5   0     FB7_16        (b)     (b)
(unused)              0       0   /\2   3     FB7_17        (b)     (b)
(unused)              0       0     0   5     FB7_18        (b)     

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$175__$INT  10: A<5>              19: DQ<15>.PIN 
  2: AS                     11: A<6>              20: DQ<14>.PIN 
  3: AUTOBOOT_OFF           12: CP_CS             21: DQ<13>.PIN 
  4: AUTO_CONFIG_DONE<0>    13: Dout1<0>          22: RESET 
  5: AUTO_CONFIG_DONE<1>    14: Dout1<1>          23: RW 
  6: A<1>                   15: Dout1<2>          24: SHUT_UP<2>/SHUT_UP<2>_CLKF 
  7: A<2>                   16: Dout1<3>          25: UDS 
  8: A<3>                   17: LAN_CS            26: autoconfig 
  9: A<4>                   18: LDS              

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
D<13>                X..........X.X..XX..X.X.X............... 8
D<14>                X..........X..X.XX.X..X.X............... 8
Dout1<2>             .X.XXXXXXXX...X..X...X.XXX.............. 15
D<15>                X..........X...XXXX...X.X............... 8
Dout1<0>             .XXXXXXXXXX.X....X...X.XXX.............. 16
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               26/28
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB8_1         (b)     
DQ<12>                2       0     0   3     FB8_2   130   I/O     I/O
DQ<14>                2       0     0   3     FB8_3   131   I/O     I/O
(unused)              0       0     0   5     FB8_4         (b)     
LAN_WRH               1       0     0   4     FB8_5   132   I/O     O
(unused)              0       0   \/2   3     FB8_6         (b)     (b)
(unused)              0       0   \/5   0     FB8_7         (b)     (b)
LAN_CS               19      14<-   0   0     FB8_8   133   I/O     O
(unused)              0       0   /\5   0     FB8_9         (b)     (b)
LAN_RD                1       0   /\2   2     FB8_10  134   I/O     O
(unused)              0       0     0   5     FB8_11        (b)     
(unused)              0       0     0   5     FB8_12        (b)     
(unused)              0       0     0   5     FB8_13        (b)     
(unused)              0       0     0   5     FB8_14        (b)     
(unused)              0       0     0   5     FB8_15        (b)     
(unused)              0       0     0   5     FB8_16        (b)     
(unused)              0       0     0   5     FB8_17        (b)     
SHUT_UP<2>/SHUT_UP<2>_CLKF
                      2       0     0   3     FB8_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$176__$INT  10: A<23>             19: LAN_BASEADR<4> 
  2: AS                     11: C1                20: LAN_BASEADR<5> 
  3: A<16>                  12: C3                21: LAN_BASEADR<6> 
  4: A<17>                  13: D<12>.PIN         22: LAN_BASEADR<7> 
  5: A<18>                  14: D<14>.PIN         23: LAN_RD_S 
  6: A<19>                  15: LAN_BASEADR<0>    24: LAN_WRH_S 
  7: A<20>                  16: LAN_BASEADR<1>    25: SHUT_UP<0> 
  8: A<21>                  17: LAN_BASEADR<2>    26: ide/ide_RSTF__$INT 
  9: A<22>                  18: LAN_BASEADR<3>   

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
DQ<12>               X...........X........................... 2
DQ<14>               X............X.......................... 2
LAN_WRH              .X.....................X................ 2
LAN_CS               .XXXXXXXXX....XXXXXXXX..XX.............. 19
LAN_RD               .X....................X................. 2
SHUT_UP<2>/SHUT_UP<2>_CLKF 
                     ..........XX............................ 2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB9  ***********************************
Number of function block inputs used/remaining:               25/29
Number of signals used by logic mapping into function block:  25
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
LAN_BASEADR<6>        6       2<- /\1   0     FB9_1         (b)     (b)
(unused)              0       0   /\2   3     FB9_2   50    I/O     I
(unused)              0       0     0   5     FB9_3   51    I/O     I
(unused)              0       0     0   5     FB9_4         (b)     
(unused)              0       0     0   5     FB9_5   52    I/O     I
(unused)              0       0     0   5     FB9_6   53    I/O     I
(unused)              0       0     0   5     FB9_7         (b)     
(unused)              0       0     0   5     FB9_8   54    I/O     I
(unused)              0       0     0   5     FB9_9         (b)     
(unused)              0       0     0   5     FB9_10        (b)     
(unused)              0       0     0   5     FB9_11  56    I/O     I
(unused)              0       0     0   5     FB9_12  57    I/O     I
(unused)              0       0     0   5     FB9_13        (b)     
(unused)              0       0     0   5     FB9_14  58    I/O     I
(unused)              0       0   \/2   3     FB9_15        (b)     (b)
LAN_BASEADR<4>        6       2<- \/1   0     FB9_16        (b)     (b)
LAN_BASEADR<2>        6       1<-   0   0     FB9_17  59    I/O     I
LAN_BASEADR<0>        6       1<-   0   0     FB9_18        (b)     (b)

Signals Used by Logic in Function Block
  1: AS                   10: D<10>.PIN         18: LAN_BASEADR<6> 
  2: AUTO_CONFIG_DONE<0>  11: D<12>.PIN         19: LDS 
  3: AUTO_CONFIG_DONE<1>  12: D<14>.PIN         20: RESET 
  4: A<1>                 13: D<8>.PIN          21: RW 
  5: A<2>                 14: DS_D              22: SHUT_UP<0> 
  6: A<3>                 15: LAN_BASEADR<0>    23: SHUT_UP<2>/SHUT_UP<2>_CLKF 
  7: A<4>                 16: LAN_BASEADR<2>    24: UDS 
  8: A<5>                 17: LAN_BASEADR<4>    25: autoconfig 
  9: A<6>                

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
LAN_BASEADR<6>       XXXXXXXXX..X.X...XXXXXXXX............... 19
LAN_BASEADR<4>       XXXXXXXXX.X..X..X.XXXXXXX............... 19
LAN_BASEADR<2>       XXXXXXXXXX...X.X..XXXXXXX............... 19
LAN_BASEADR<0>       XXXXXXXXX...XXX...XXXXXXX............... 19
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB10 ***********************************
Number of function block inputs used/remaining:               20/34
Number of signals used by logic mapping into function block:  20
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB10_1        (b)     
DQ<1>                 2       0     0   3     FB10_2  117   I/O     I/O
DQ<0>                 2       0     0   3     FB10_3  118   I/O     I/O
(unused)              0       0     0   5     FB10_4        (b)     
DQ<3>                 2       0     0   3     FB10_5  119   I/O     I/O
DQ<2>                 2       0     0   3     FB10_6  120   I/O     I/O
(unused)              0       0     0   5     FB10_7        (b)     
DQ<5>                 2       0     0   3     FB10_8  121   I/O     I/O
SLAVE_OBUF__$INT      2       0     0   3     FB10_9        (b)     (b)
DQ<4>                 2       0     0   3     FB10_10 124   I/O     I/O
DQ<7>                 2       0     0   3     FB10_11 125   I/O     I/O
DQ<6>                 2       0     0   3     FB10_12 126   I/O     I/O
ROM_OE_S              2       0     0   3     FB10_13       (b)     (b)
DQ<8>                 2       0     0   3     FB10_14 128   I/O     I/O
IDE_W_S               2       0     0   3     FB10_15       (b)     (b)
IDE_R_S               2       0     0   3     FB10_16       (b)     (b)
DQ<10>                2       0     0   3     FB10_17 129   I/O     I/O
IDE_ENABLE            3       0     0   2     FB10_18       (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$176__$INT   8: D<3>.PIN          15: LAN_CS 
  2: AS                      9: D<4>.PIN          16: RESET 
  3: CP_CS                  10: D<5>.PIN          17: RW 
  4: D<0>.PIN               11: D<6>.PIN          18: SHUT_UP<2>/SHUT_UP<2>_CLKF 
  5: D<10>.PIN              12: D<7>.PIN          19: autoconfig 
  6: D<1>.PIN               13: D<8>.PIN          20: ide 
  7: D<2>.PIN               14: IDE_ENABLE       

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
DQ<1>                X....X.................................. 2
DQ<0>                X..X.................................... 2
DQ<3>                X......X................................ 2
DQ<2>                X.....X................................. 2
DQ<5>                X........X.............................. 2
SLAVE_OBUF__$INT     .XX...........X...XX.................... 5
DQ<4>                X.......X............................... 2
DQ<7>                X..........X............................ 2
DQ<6>                X.........X............................. 2
ROM_OE_S             .X...........X.XXX.X.................... 6
DQ<8>                X...........X........................... 2
IDE_W_S              .X.............XXX.X.................... 5
IDE_R_S              .X...........X.XXX.X.................... 6
DQ<10>               X...X................................... 2
IDE_ENABLE           .X...........X.XXX.X.................... 6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB11 ***********************************
Number of function block inputs used/remaining:               26/28
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\1   4     FB11_1        (b)     (b)
(unused)              0       0     0   5     FB11_2        (b)     
(unused)              0       0     0   5     FB11_3  60    I/O     I
(unused)              0       0     0   5     FB11_4        (b)     
(unused)              0       0     0   5     FB11_5  61    I/O     I
(unused)              0       0     0   5     FB11_6        (b)     
(unused)              0       0     0   5     FB11_7        (b)     
(unused)              0       0     0   5     FB11_8        (b)     
(unused)              0       0     0   5     FB11_9        (b)     
(unused)              0       0     0   5     FB11_10 64    I/O     I
(unused)              0       0     0   5     FB11_11 66    I/O     I
ROM_B<0>              0       0   \/1   4     FB11_12 68    I/O     O
IDE_BASEADR<7>        6       1<-   0   0     FB11_13       (b)     (b)
ROM_B<1>              0       0   \/1   4     FB11_14 69    I/O     O
IDE_BASEADR<6>        6       1<-   0   0     FB11_15       (b)     (b)
IDE_BASEADR<5>        6       1<-   0   0     FB11_16       (b)     (b)
CP_WE                 1       0   /\1   3     FB11_17 70    I/O     O
IDE_BASEADR<4>        6       1<-   0   0     FB11_18       (b)     (b)

Signals Used by Logic in Function Block
  1: AS                   10: CP_WE_S           19: IDE_BASEADR<7> 
  2: AUTO_CONFIG_DONE<0>  11: D<12>.PIN         20: LDS 
  3: AUTO_CONFIG_DONE<1>  12: D<13>.PIN         21: RESET 
  4: A<1>                 13: D<14>.PIN         22: RW 
  5: A<2>                 14: D<15>.PIN         23: SHUT_UP<2> 
  6: A<3>                 15: DS_D              24: SHUT_UP<2>/SHUT_UP<2>_CLKF 
  7: A<4>                 16: IDE_BASEADR<4>    25: UDS 
  8: A<5>                 17: IDE_BASEADR<5>    26: autoconfig 
  9: A<6>                 18: IDE_BASEADR<6>   

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
ROM_B<0>             ........................................ 0
IDE_BASEADR<7>       XXXXXXXXX....XX...XXXXXXXX.............. 19
ROM_B<1>             ........................................ 0
IDE_BASEADR<6>       XXXXXXXXX...X.X..X.XXXXXXX.............. 19
IDE_BASEADR<5>       XXXXXXXXX..X..X.X..XXXXXXX.............. 19
CP_WE                X........X.............................. 2
IDE_BASEADR<4>       XXXXXXXXX.X...XX...XXXXXXX.............. 19
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB12 ***********************************
Number of function block inputs used/remaining:               26/28
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
LAN_BASEADR<7>        6       2<- /\1   0     FB12_1        (b)     (b)
LAN_CFG<4>            0       0   /\2   3     FB12_2  110   I/O     O
(unused)              0       0     0   5     FB12_3  111   I/O     
(unused)              0       0     0   5     FB12_4        (b)     
DQ<15>                2       0     0   3     FB12_5  112   I/O     I/O
(unused)              0       0     0   5     FB12_6        (b)     
(unused)              0       0     0   5     FB12_7        (b)     
DQ<13>                2       0     0   3     FB12_8  113   I/O     I/O
(unused)              0       0     0   5     FB12_9        (b)     
DQ<11>                2       0     0   3     FB12_10 115   I/O     I/O
(unused)              0       0     0   5     FB12_11       (b)     
DQ<9>                 2       0     0   3     FB12_12 116   I/O     I/O
(unused)              0       0     0   5     FB12_13       (b)     
(unused)              0       0     0   5     FB12_14       (b)     
(unused)              0       0   \/2   3     FB12_15       (b)     (b)
LAN_BASEADR<5>        6       2<- \/1   0     FB12_16       (b)     (b)
LAN_BASEADR<3>        6       1<-   0   0     FB12_17       (b)     (b)
LAN_BASEADR<1>        6       1<-   0   0     FB12_18       (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$176__$INT  10: A<6>              19: LAN_BASEADR<7> 
  2: AS                     11: D<11>.PIN         20: LDS 
  3: AUTO_CONFIG_DONE<0>    12: D<13>.PIN         21: RESET 
  4: AUTO_CONFIG_DONE<1>    13: D<15>.PIN         22: RW 
  5: A<1>                   14: D<9>.PIN          23: SHUT_UP<0> 
  6: A<2>                   15: DS_D              24: SHUT_UP<2>/SHUT_UP<2>_CLKF 
  7: A<3>                   16: LAN_BASEADR<1>    25: UDS 
  8: A<4>                   17: LAN_BASEADR<3>    26: autoconfig 
  9: A<5>                   18: LAN_BASEADR<5>   

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
LAN_BASEADR<7>       .XXXXXXXXX..X.X...XXXXXXXX.............. 19
LAN_CFG<4>           ........................................ 0
DQ<15>               X...........X........................... 2
DQ<13>               X..........X............................ 2
DQ<11>               X.........X............................. 2
DQ<9>                X............X.......................... 2
LAN_BASEADR<5>       .XXXXXXXXX.X..X..X.XXXXXXX.............. 19
LAN_BASEADR<3>       .XXXXXXXXXX...X.X..XXXXXXX.............. 19
LAN_BASEADR<1>       .XXXXXXXXX...XXX...XXXXXXX.............. 19
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB13 ***********************************
Number of function block inputs used/remaining:               25/29
Number of signals used by logic mapping into function block:  25
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\2   3     FB13_1        (b)     (b)
CP_RD                 1       0     0   4     FB13_2  71    I/O     O
(unused)              0       0     0   5     FB13_3        (b)     
(unused)              0       0     0   5     FB13_4        (b)     
(unused)              0       0     0   5     FB13_5        (b)     
(unused)              0       0     0   5     FB13_6        (b)     
(unused)              0       0     0   5     FB13_7        (b)     
(unused)              0       0     0   5     FB13_8  74    I/O     
(unused)              0       0     0   5     FB13_9        (b)     
(unused)              0       0     0   5     FB13_10       (b)     
(unused)              0       0     0   5     FB13_11 75    I/O     I
(unused)              0       0     0   5     FB13_12       (b)     
(unused)              0       0     0   5     FB13_13       (b)     
LAN_WRL               1       0     0   4     FB13_14 76    I/O     O
(unused)              0       0   \/1   4     FB13_15 77    I/O     (b)
CP_BASEADR<4>         6       1<-   0   0     FB13_16       (b)     (b)
CP_BASEADR<3>         6       1<-   0   0     FB13_17 78    I/O     (b)
CP_BASEADR<2>         6       2<- /\1   0     FB13_18       (b)     (b)

Signals Used by Logic in Function Block
  1: AS                   10: CP_BASEADR<2>     18: LAN_WRL_S 
  2: AUTO_CONFIG_DONE<0>  11: CP_BASEADR<3>     19: LDS 
  3: AUTO_CONFIG_DONE<1>  12: CP_BASEADR<4>     20: RESET 
  4: A<1>                 13: CP_RD_S           21: RW 
  5: A<2>                 14: D<10>.PIN         22: SHUT_UP<1> 
  6: A<3>                 15: D<11>.PIN         23: SHUT_UP<2>/SHUT_UP<2>_CLKF 
  7: A<4>                 16: D<12>.PIN         24: UDS 
  8: A<5>                 17: DS_D              25: autoconfig 
  9: A<6>                

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
CP_RD                X...........X........................... 2
LAN_WRL              X................X...................... 2
CP_BASEADR<4>        XXXXXXXXX..X...XX.XXXXXXX............... 19
CP_BASEADR<3>        XXXXXXXXX.X...X.X.XXXXXXX............... 19
CP_BASEADR<2>        XXXXXXXXXX...X..X.XXXXXXX............... 19
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB14 ***********************************
Number of function block inputs used/remaining:               26/28
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\1   4     FB14_1        (b)     (b)
(unused)              0       0     0   5     FB14_2        (b)     
OVR                   1       0     0   4     FB14_3  100   I/O     O
(unused)              0       0     0   5     FB14_4        (b)     
(unused)              0       0     0   5     FB14_5  101   I/O     
(unused)              0       0     0   5     FB14_6  102   I/O     I
(unused)              0       0     0   5     FB14_7        (b)     
(unused)              0       0     0   5     FB14_8  103   I/O     I
(unused)              0       0     0   5     FB14_9        (b)     
(unused)              0       0     0   5     FB14_10 104   I/O     I
CFOUT                 1       0     0   4     FB14_11 105   I/O     O
(unused)              0       0     0   5     FB14_12       (b)     
(unused)              0       0     0   5     FB14_13       (b)     
SLAVE                 2       0     0   3     FB14_14 106   I/O     O
OWN                   1       0     0   4     FB14_15 107   I/O     O
ide/ide_RSTF__$INT    1       0   \/1   3     FB14_16       (b)     (b)
CP_BASEADR<1>         6       1<-   0   0     FB14_17       (b)     (b)
CP_BASEADR<0>         6       1<-   0   0     FB14_18       (b)     (b)

Signals Used by Logic in Function Block
  1: AS                   10: BERR              19: RESET 
  2: AUTO_CONFIG_DONE<0>  11: CP_BASEADR<0>     20: RW 
  3: AUTO_CONFIG_DONE<1>  12: CP_BASEADR<1>     21: SHUT_UP<1> 
  4: A<1>                 13: CP_CS             22: SHUT_UP<2>/SHUT_UP<2>_CLKF 
  5: A<2>                 14: D<8>.PIN          23: SLAVE_OBUF__$INT 
  6: A<3>                 15: D<9>.PIN          24: UDS 
  7: A<4>                 16: DS_D              25: autoconfig 
  8: A<5>                 17: LAN_CS            26: ide 
  9: A<6>                 18: LDS              

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
OVR                  X........................X.............. 2
CFOUT                .XX..................................... 2
SLAVE                X...........X...X.......XX.............. 5
OWN                  ......................X................. 1
ide/ide_RSTF__$INT   .........X........X..................... 2
CP_BASEADR<1>        XXXXXXXXX..X..XX.XXXXX.XX............... 19
CP_BASEADR<0>        XXXXXXXXX.X..X.X.XXXXX.XX............... 19
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB15 ***********************************
Number of function block inputs used/remaining:               25/29
Number of signals used by logic mapping into function block:  25
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\2   3     FB15_1        (b)     (b)
(unused)              0       0     0   5     FB15_2  79    I/O     
(unused)              0       0     0   5     FB15_3  80    I/O     I
(unused)              0       0     0   5     FB15_4        (b)     
(unused)              0       0     0   5     FB15_5        (b)     
(unused)              0       0     0   5     FB15_6        (b)     
(unused)              0       0     0   5     FB15_7        (b)     
(unused)              0       0     0   5     FB15_8  81    I/O     I
(unused)              0       0     0   5     FB15_9        (b)     
(unused)              0       0     0   5     FB15_10 82    I/O     I
(unused)              0       0     0   5     FB15_11 83    I/O     I
DTACK                 1       0     0   4     FB15_12 85    I/O     O
(unused)              0       0     0   5     FB15_13       (b)     
(unused)              0       0     0   5     FB15_14 86    I/O     I
(unused)              0       0   \/1   4     FB15_15 87    I/O     I
CP_BASEADR<7>         6       1<-   0   0     FB15_16       (b)     (b)
CP_BASEADR<6>         6       1<-   0   0     FB15_17 88    I/O     I
CP_BASEADR<5>         6       2<- /\1   0     FB15_18       (b)     (b)

Signals Used by Logic in Function Block
  1: AS                   10: CP_BASEADR<5>     18: LDS 
  2: AUTO_CONFIG_DONE<0>  11: CP_BASEADR<6>     19: RESET 
  3: AUTO_CONFIG_DONE<1>  12: CP_BASEADR<7>     20: RW 
  4: A<1>                 13: D<13>.PIN         21: SHUT_UP<1> 
  5: A<2>                 14: D<14>.PIN         22: SHUT_UP<2>/SHUT_UP<2>_CLKF 
  6: A<3>                 15: D<15>.PIN         23: UDS 
  7: A<4>                 16: DS_D              24: autoconfig 
  8: A<5>                 17: IDE_WAIT          25: ide 
  9: A<6>                

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
DTACK                X...............X.......X............... 3
CP_BASEADR<7>        XXXXXXXXX..X..XX.XXXXXXX................ 19
CP_BASEADR<6>        XXXXXXXXX.X..X.X.XXXXXXX................ 19
CP_BASEADR<5>        XXXXXXXXXX..X..X.XXXXXXX................ 19
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB16 ***********************************
Number of function block inputs used/remaining:               13/41
Number of signals used by logic mapping into function block:  13
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB16_1        (b)     
(unused)              0       0     0   5     FB16_2  91    I/O     I
(unused)              0       0     0   5     FB16_3  92    I/O     I
(unused)              0       0     0   5     FB16_4        (b)     
(unused)              0       0     0   5     FB16_5  93    I/O     
(unused)              0       0     0   5     FB16_6  94    I/O     I
(unused)              0       0     0   5     FB16_7        (b)     
(unused)              0       0     0   5     FB16_8  95    I/O     I
(unused)              0       0     0   5     FB16_9        (b)     
(unused)              0       0     0   5     FB16_10 96    I/O     
(unused)              0       0     0   5     FB16_11 97    I/O     I
(unused)              0       0     0   5     FB16_12 98    I/O     I
(unused)              0       0     0   5     FB16_13       (b)     
(unused)              0       0     0   5     FB16_14       (b)     
(unused)              0       0     0   5     FB16_15       (b)     
(unused)              0       0     0   5     FB16_16       (b)     
(unused)              0       0     0   5     FB16_17       (b)     
autoconfig            4       0     0   1     FB16_18       (b)     (b)

Signals Used by Logic in Function Block
  1: AS                    6: A<18>             10: A<22> 
  2: AUTO_CONFIG_DONE<0>   7: A<19>             11: A<23> 
  3: AUTO_CONFIG_DONE<1>   8: A<20>             12: CFIN 
  4: A<16>                 9: A<21>             13: ide/ide_RSTF__$INT 
  5: A<17>               

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
autoconfig           XXXXXXXXXXXXX........................... 13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$FX_DC$175__$INT <= ((NOT RW)
	OR (UDS AND LDS)
	OR (NOT LAN_CS AND NOT autoconfig AND CP_CS));


$OpTx$FX_DC$176__$INT <= ((RW)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));

FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_D(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
AUTO_CONFIG_DONE_D(0) <= ((AS AND RESET AND AUTO_CONFIG_DONE_CYCLE(0))
	OR (NOT AS AND RESET AND AUTO_CONFIG_DONE(0)));

FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_D(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
AUTO_CONFIG_DONE_D(1) <= ((AS AND RESET AND AUTO_CONFIG_DONE_CYCLE(1))
	OR (NOT AS AND RESET AND AUTO_CONFIG_DONE(1)));

FTCPE_AUTO_CONFIG_DONE_CYCLE0: FTCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_T(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
AUTO_CONFIG_DONE_CYCLE_T(0) <= ((NOT AS AND NOT RW AND RESET AND A(2) AND autoconfig AND NOT A(5) AND 
	NOT A(4) AND NOT A(1) AND A(6) AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
	A(6) AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
	A(6) AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND AUTO_CONFIG_DONE_CYCLE(0))
	OR (NOT AS AND NOT RW AND RESET AND A(2) AND autoconfig AND NOT A(5) AND 
	NOT A(4) AND NOT A(1) AND A(6) AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
	A(6) AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
	A(6) AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
	A(6) AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
	A(6) AND NOT LDS AND DS_D AND A(3)));

FTCPE_AUTO_CONFIG_DONE_CYCLE1: FTCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_T(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
AUTO_CONFIG_DONE_CYCLE_T(1) <= ((NOT AS AND NOT RW AND RESET AND A(2) AND 
	AUTO_CONFIG_DONE_CYCLE(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT LDS AND 
	DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE_CYCLE(0) AND SHUT_UP(1) AND 
	autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT UDS AND DS_D AND 
	A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE_CYCLE(0) AND SHUT_UP(0) AND 
	autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT UDS AND DS_D AND 
	A(3))
	OR (NOT RESET AND AUTO_CONFIG_DONE_CYCLE(1))
	OR (NOT AS AND NOT RW AND RESET AND A(2) AND 
	AUTO_CONFIG_DONE_CYCLE(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT UDS AND 
	DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE_CYCLE(0) AND SHUT_UP(2) AND 
	autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT UDS AND DS_D AND 
	A(3))
	OR (NOT AS AND NOT RW AND RESET AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE_CYCLE(0) AND SHUT_UP(2) AND 
	autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT LDS AND DS_D AND 
	A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE_CYCLE(0) AND SHUT_UP(1) AND 
	autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT LDS AND DS_D AND 
	A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE_CYCLE(0) AND SHUT_UP(0) AND 
	autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT LDS AND DS_D AND 
	A(3)));


A_LAN(0) <= A(1);


A_LAN(1) <= A(2);


A_LAN(2) <= A(3);


A_LAN(3) <= A(4);


A_LAN(4) <= A(5);


A_LAN(5) <= A(6);


A_LAN(6) <= A(7);


A_LAN(7) <= A(8);


A_LAN(8) <= A(9);


A_LAN(9) <= A(10);


A_LAN(10) <= A(11);


A_LAN(11) <= A(12);


A_LAN(12) <= A(13);


A_LAN(13) <= A(14);


CFOUT <= NOT ((AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(0)));

FTCPE_CP_BASEADR0: FTCPE port map (CP_BASEADR(0),CP_BASEADR_T(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
CP_BASEADR_T(0) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(0) AND NOT A(1) AND A(6) AND NOT D(8).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT CP_BASEADR(0))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(0) AND NOT A(1) AND A(6) AND D(8).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(0) AND NOT A(1) AND A(6) AND D(8).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(0) AND NOT A(1) AND A(6) AND NOT D(8).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_CP_BASEADR1: FTCPE port map (CP_BASEADR(1),CP_BASEADR_T(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
CP_BASEADR_T(1) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(1) AND NOT A(1) AND A(6) AND NOT D(9).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT CP_BASEADR(1))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(1) AND NOT A(1) AND A(6) AND D(9).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(1) AND NOT A(1) AND A(6) AND D(9).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(1) AND NOT A(1) AND A(6) AND NOT D(9).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_CP_BASEADR2: FTCPE port map (CP_BASEADR(2),CP_BASEADR_T(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
CP_BASEADR_T(2) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(2) AND NOT A(1) AND A(6) AND NOT D(10).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(2) AND NOT A(1) AND A(6) AND NOT D(10).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT CP_BASEADR(2))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(2) AND NOT A(1) AND A(6) AND D(10).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(2) AND NOT A(1) AND A(6) AND D(10).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_CP_BASEADR3: FTCPE port map (CP_BASEADR(3),CP_BASEADR_T(3),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
CP_BASEADR_T(3) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(3) AND NOT A(1) AND A(6) AND NOT D(11).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT CP_BASEADR(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(3) AND NOT A(1) AND A(6) AND D(11).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(3) AND NOT A(1) AND A(6) AND D(11).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(3) AND NOT A(1) AND A(6) AND NOT D(11).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_CP_BASEADR4: FTCPE port map (CP_BASEADR(4),CP_BASEADR_T(4),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
CP_BASEADR_T(4) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(4) AND NOT A(1) AND A(6) AND NOT D(12).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT CP_BASEADR(4))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(4) AND NOT A(1) AND A(6) AND D(12).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(4) AND NOT A(1) AND A(6) AND D(12).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(4) AND NOT A(1) AND A(6) AND NOT D(12).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_CP_BASEADR5: FTCPE port map (CP_BASEADR(5),CP_BASEADR_T(5),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
CP_BASEADR_T(5) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(5) AND NOT A(1) AND A(6) AND NOT D(13).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(5) AND NOT A(1) AND A(6) AND NOT D(13).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT CP_BASEADR(5))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(5) AND NOT A(1) AND A(6) AND D(13).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(5) AND NOT A(1) AND A(6) AND D(13).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_CP_BASEADR6: FTCPE port map (CP_BASEADR(6),CP_BASEADR_T(6),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
CP_BASEADR_T(6) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(6) AND NOT A(1) AND A(6) AND NOT D(14).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT CP_BASEADR(6))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(6) AND NOT A(1) AND A(6) AND D(14).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(6) AND NOT A(1) AND A(6) AND D(14).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(6) AND NOT A(1) AND A(6) AND NOT D(14).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_CP_BASEADR7: FTCPE port map (CP_BASEADR(7),CP_BASEADR_T(7),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
CP_BASEADR_T(7) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(7) AND NOT A(1) AND A(6) AND NOT D(15).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT CP_BASEADR(7))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(7) AND NOT A(1) AND A(6) AND D(15).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT CP_BASEADR(7) AND NOT A(1) AND A(6) AND D(15).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND SHUT_UP(1) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	CP_BASEADR(7) AND NOT A(1) AND A(6) AND NOT D(15).PIN AND NOT LDS AND DS_D AND A(3)));

FDCPE_CP_CS: FDCPE port map (CP_CS,CP_CS_D,NOT AS,'0',NOT ide/ide_RSTF__$INT);
CP_CS_D <= ((SHUT_UP(1))
	OR (CP_BASEADR(4) AND NOT A(20))
	OR (CP_BASEADR(5) AND NOT A(21))
	OR (NOT CP_BASEADR(5) AND A(21))
	OR (CP_BASEADR(6) AND NOT A(22))
	OR (NOT CP_BASEADR(6) AND A(22))
	OR (EXP26_.EXP)
	OR (CP_BASEADR(2) AND NOT A(18))
	OR (NOT CP_BASEADR(2) AND A(18))
	OR (CP_BASEADR(3) AND NOT A(19))
	OR (NOT CP_BASEADR(3) AND A(19))
	OR (NOT CP_BASEADR(4) AND A(20))
	OR (CP_BASEADR(7) AND NOT A(23))
	OR (NOT CP_BASEADR(7) AND A(23)));


CP_RD <= NOT ((NOT AS AND NOT CP_RD_S));

FDCPE_CP_RD_S: FDCPE port map (CP_RD_S,CP_RD_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
CP_RD_S_D <= ((RW AND RESET AND NOT UDS AND NOT CP_CS)
	OR (RW AND RESET AND NOT LDS AND NOT CP_CS));


CP_WE <= NOT ((NOT AS AND NOT CP_WE_S));

FDCPE_CP_WE_S: FDCPE port map (CP_WE_S,CP_WE_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
CP_WE_S_D <= ((NOT RW AND RESET AND NOT UDS AND NOT CP_CS)
	OR (NOT RW AND RESET AND NOT LDS AND NOT CP_CS));


D_I(0) <= ((NOT RW)
	OR (DQ(0).PIN)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
D_OE(0) <= NOT $OpTx$FX_DC$175__$INT;


D_I(1) <= ((NOT RW)
	OR (DQ(1).PIN)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
D_OE(1) <= NOT $OpTx$FX_DC$175__$INT;


D_I(2) <= ((NOT RW)
	OR (DQ(2).PIN)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
D_OE(2) <= NOT $OpTx$FX_DC$175__$INT;


D_I(3) <= ((NOT RW)
	OR (DQ(3).PIN)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
D_OE(3) <= NOT $OpTx$FX_DC$175__$INT;


D_I(4) <= ((NOT RW)
	OR (DQ(4).PIN)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
D_OE(4) <= NOT $OpTx$FX_DC$175__$INT;


D_I(5) <= ((NOT RW)
	OR (DQ(5).PIN)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
D_OE(5) <= NOT $OpTx$FX_DC$175__$INT;


D_I(6) <= ((NOT RW)
	OR (DQ(6).PIN)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
D_OE(6) <= NOT $OpTx$FX_DC$175__$INT;


D_I(7) <= ((NOT RW)
	OR (DQ(7).PIN)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
D_OE(7) <= NOT $OpTx$FX_DC$175__$INT;


D_I(8) <= ((NOT RW)
	OR (DQ(8).PIN)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));
D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
D_OE(8) <= NOT $OpTx$FX_DC$175__$INT;


D_I(9) <= ((NOT RW)
	OR (DQ(9).PIN)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));
D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
D_OE(9) <= NOT $OpTx$FX_DC$175__$INT;


D_I(10) <= ((NOT RW)
	OR (DQ(10).PIN)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));
D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
D_OE(10) <= NOT $OpTx$FX_DC$175__$INT;


D_I(11) <= ((NOT RW)
	OR (DQ(11).PIN)
	OR (NOT LAN_CS AND CP_CS)
	OR (UDS AND LDS));
D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
D_OE(11) <= NOT $OpTx$FX_DC$175__$INT;


D_I(12) <= ((RW AND LAN_CS AND NOT LDS AND DQ(12).PIN)
	OR (RW AND NOT UDS AND DQ(12).PIN AND NOT CP_CS)
	OR (RW AND LAN_CS AND NOT UDS AND DQ(12).PIN)
	OR (NOT RW AND Dout1(0))
	OR (NOT LAN_CS AND Dout1(0) AND CP_CS)
	OR (Dout1(0) AND UDS AND LDS)
	OR (RW AND NOT LDS AND DQ(12).PIN AND NOT CP_CS));
D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
D_OE(12) <= NOT $OpTx$FX_DC$175__$INT;


D_I(13) <= ((RW AND LAN_CS AND NOT UDS AND DQ(13).PIN)
	OR (RW AND LAN_CS AND NOT LDS AND DQ(13).PIN)
	OR (RW AND NOT UDS AND DQ(13).PIN AND NOT CP_CS)
	OR (NOT RW AND Dout1(1))
	OR (NOT LAN_CS AND Dout1(1) AND CP_CS)
	OR (Dout1(1) AND UDS AND LDS)
	OR (RW AND NOT LDS AND DQ(13).PIN AND NOT CP_CS));
D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
D_OE(13) <= NOT $OpTx$FX_DC$175__$INT;


D_I(14) <= ((RW AND LAN_CS AND NOT UDS AND DQ(14).PIN)
	OR (RW AND LAN_CS AND NOT LDS AND DQ(14).PIN)
	OR (RW AND NOT UDS AND DQ(14).PIN AND NOT CP_CS)
	OR (NOT RW AND Dout1(2))
	OR (NOT LAN_CS AND Dout1(2) AND CP_CS)
	OR (Dout1(2) AND UDS AND LDS)
	OR (RW AND NOT LDS AND DQ(14).PIN AND NOT CP_CS));
D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
D_OE(14) <= NOT $OpTx$FX_DC$175__$INT;


D_I(15) <= ((RW AND LAN_CS AND NOT UDS AND DQ(15).PIN)
	OR (RW AND LAN_CS AND NOT LDS AND DQ(15).PIN)
	OR (RW AND NOT UDS AND DQ(15).PIN AND NOT CP_CS)
	OR (NOT RW AND Dout1(3))
	OR (NOT LAN_CS AND Dout1(3) AND CP_CS)
	OR (Dout1(3) AND UDS AND LDS)
	OR (RW AND NOT LDS AND DQ(15).PIN AND NOT CP_CS));
D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
D_OE(15) <= NOT $OpTx$FX_DC$175__$INT;


DQ_I(0) <= D(0).PIN;
DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z';
DQ_OE(0) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(1) <= D(1).PIN;
DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z';
DQ_OE(1) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(2) <= D(2).PIN;
DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z';
DQ_OE(2) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(3) <= D(3).PIN;
DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z';
DQ_OE(3) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(4) <= D(4).PIN;
DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z';
DQ_OE(4) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(5) <= D(5).PIN;
DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z';
DQ_OE(5) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(6) <= D(6).PIN;
DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z';
DQ_OE(6) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(7) <= D(7).PIN;
DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z';
DQ_OE(7) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(8) <= D(8).PIN;
DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z';
DQ_OE(8) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(9) <= D(9).PIN;
DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z';
DQ_OE(9) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(10) <= D(10).PIN;
DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z';
DQ_OE(10) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(11) <= D(11).PIN;
DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z';
DQ_OE(11) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(12) <= D(12).PIN;
DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z';
DQ_OE(12) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(13) <= D(13).PIN;
DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z';
DQ_OE(13) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(14) <= D(14).PIN;
DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z';
DQ_OE(14) <= NOT $OpTx$FX_DC$176__$INT;


DQ_I(15) <= D(15).PIN;
DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z';
DQ_OE(15) <= NOT $OpTx$FX_DC$176__$INT;

FDCPE_DS_D: FDCPE port map (DS_D,DS_D_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
DS_D_D <= (UDS AND LDS);


DTACK_I <= '0';
DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
DTACK_OE <= (NOT AS AND ide AND IDE_WAIT);

FDCPE_Dout10: FDCPE port map (Dout1(0),Dout1_D(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
Dout1_D(0) <= ((EXP38_.EXP)
	OR (RESET AND NOT Dout1(0) AND UDS AND LDS)
	OR (NOT AS AND RESET AND A(2) AND autoconfig AND A(5) AND NOT A(4) AND 
	NOT A(6) AND NOT LDS AND NOT A(3))
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND A(4) AND 
	NOT A(6) AND NOT LDS AND A(3))
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	A(6) AND NOT LDS AND NOT A(3))
	OR (NOT AS AND RESET AND autoconfig AND NOT A(5) AND A(4) AND A(1) AND 
	NOT A(6) AND NOT LDS AND A(3))
	OR (EXP41_.EXP)
	OR (NOT AS AND RESET AND A(2) AND autoconfig AND A(5) AND NOT A(4) AND 
	NOT A(6) AND NOT UDS AND NOT A(3))
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND A(4) AND 
	NOT A(6) AND NOT UDS AND A(3))
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	A(6) AND NOT UDS AND NOT A(3))
	OR (NOT AS AND RESET AND autoconfig AND NOT A(5) AND A(4) AND A(1) AND 
	NOT A(6) AND NOT UDS AND A(3))
	OR (NOT AS AND RESET AND A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	autoconfig AND NOT A(5) AND NOT A(1) AND NOT A(6) AND NOT LDS AND NOT A(3))
	OR (AS AND RESET AND NOT Dout1(0))
	OR (RESET AND NOT autoconfig AND NOT Dout1(0))
	OR (NOT AS AND RESET AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND 
	NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(6) AND NOT UDS AND NOT A(3))
	OR (NOT AS AND RESET AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND 
	NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(6) AND NOT LDS AND NOT A(3)));

FDCPE_Dout11: FDCPE port map (Dout1(1),Dout1_D(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
Dout1_D(1) <= ((A_LAN_5_OBUF$BUF0.EXP)
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT UDS AND NOT A(3))
	OR (NOT AS AND RESET AND A(2) AND autoconfig AND NOT A(5) AND A(4) AND 
	NOT A(6) AND NOT UDS AND A(3))
	OR (NOT AS AND RESET AND A(2) AND autoconfig AND NOT A(5) AND A(4) AND 
	NOT A(6) AND NOT LDS AND A(3))
	OR (NOT AS AND RESET AND autoconfig AND NOT A(5) AND A(4) AND NOT A(1) AND 
	NOT A(6) AND NOT UDS AND A(3))
	OR (NOT AS AND RESET AND autoconfig AND NOT A(5) AND A(4) AND NOT A(1) AND 
	NOT A(6) AND NOT LDS AND A(3))
	OR (EXP23_.EXP)
	OR (NOT AS AND RESET AND A(2) AND AUTO_CONFIG_DONE(1) AND 
	autoconfig AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND NOT LDS)
	OR (NOT AS AND RESET AND A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	autoconfig AND NOT A(4) AND NOT A(1) AND NOT A(6) AND NOT LDS AND NOT A(3))
	OR (NOT AS AND RESET AND A(2) AND autoconfig AND A(5) AND NOT A(4) AND 
	NOT A(1) AND NOT A(6) AND NOT LDS AND NOT A(3))
	OR (NOT AS AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	autoconfig AND NOT A(5) AND A(1) AND NOT A(6) AND NOT LDS AND NOT A(3))
	OR (NOT AS AND RESET AND AUTO_CONFIG_DONE(1) AND autoconfig AND 
	NOT A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND NOT LDS AND NOT A(3))
	OR (AS AND RESET AND NOT Dout1(1))
	OR (RESET AND NOT autoconfig AND NOT Dout1(1))
	OR (RESET AND NOT Dout1(1) AND UDS AND LDS)
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LDS AND NOT A(3)));

FDCPE_Dout12: FDCPE port map (Dout1(2),Dout1_D(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
Dout1_D(2) <= ((EXP34_.EXP)
	OR (AS AND RESET AND NOT Dout1(2))
	OR (RESET AND NOT autoconfig AND NOT Dout1(2))
	OR (RESET AND NOT Dout1(2) AND UDS AND LDS)
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	A(6) AND NOT UDS AND NOT A(3))
	OR (NOT AS AND RESET AND AUTO_CONFIG_DONE(0) AND autoconfig AND 
	NOT A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND NOT UDS AND NOT A(3))
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	A(1) AND NOT UDS AND NOT A(3))
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	A(1) AND NOT LDS AND NOT A(3))
	OR (NOT AS AND RESET AND A(2) AND autoconfig AND A(5) AND NOT A(4) AND 
	A(1) AND NOT A(6) AND NOT UDS AND NOT A(3))
	OR (NOT AS AND RESET AND A(2) AND autoconfig AND A(5) AND NOT A(4) AND 
	A(1) AND NOT A(6) AND NOT LDS AND NOT A(3))
	OR (NOT AS AND RESET AND A(2) AND autoconfig AND NOT A(5) AND A(4) AND 
	A(1) AND NOT A(6) AND NOT LDS AND NOT A(3))
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	A(6) AND NOT LDS AND NOT A(3))
	OR (NOT AS AND RESET AND AUTO_CONFIG_DONE(1) AND autoconfig AND 
	NOT A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND NOT UDS AND NOT A(3))
	OR (NOT AS AND RESET AND AUTO_CONFIG_DONE(1) AND autoconfig AND 
	NOT A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND NOT LDS AND NOT A(3))
	OR (NOT AS AND RESET AND AUTO_CONFIG_DONE(0) AND autoconfig AND 
	NOT A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND NOT LDS AND NOT A(3)));

FDCPE_Dout13: FDCPE port map (Dout1(3),Dout1_D(3),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
Dout1_D(3) <= ((LAN_WRL_S.EXP)
	OR (NOT AS AND RESET AND A(2) AND autoconfig AND NOT A(5) AND A(4) AND 
	A(1) AND NOT A(6) AND NOT UDS)
	OR (NOT AS AND RESET AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND 
	NOT A(5) AND A(1) AND NOT A(6) AND NOT UDS AND NOT A(3))
	OR (NOT AS AND RESET AND A(2) AND autoconfig AND A(5) AND NOT A(4) AND 
	NOT A(1) AND NOT A(6) AND NOT LDS AND NOT A(3))
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND A(4) AND 
	NOT A(1) AND NOT A(6) AND NOT UDS AND A(3))
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND A(4) AND 
	NOT A(1) AND NOT A(6) AND NOT LDS AND A(3))
	OR (RESET AND NOT Dout1(3) AND UDS AND LDS)
	OR (NOT AS AND RESET AND A(2) AND autoconfig AND NOT A(5) AND A(4) AND 
	A(1) AND NOT A(6) AND NOT LDS)
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	A(6) AND NOT UDS AND NOT A(3))
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	A(6) AND NOT LDS AND NOT A(3))
	OR (NOT AS AND RESET AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND 
	NOT A(5) AND A(1) AND NOT A(6) AND NOT LDS AND NOT A(3))
	OR (AS AND RESET AND NOT Dout1(3))
	OR (RESET AND NOT autoconfig AND NOT Dout1(3))
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND A(1) AND 
	NOT A(6) AND NOT UDS AND NOT A(3))
	OR (NOT AS AND RESET AND NOT A(2) AND autoconfig AND NOT A(5) AND A(1) AND 
	NOT A(6) AND NOT LDS AND NOT A(3)));










































































IDE_A(0) <= A(9);


IDE_A(1) <= A(10);


IDE_A(2) <= A(11);

FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
IDE_BASEADR_T(0) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(0) AND NOT A(1) AND A(6) AND NOT D(8).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT IDE_BASEADR(0))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(0) AND NOT A(1) AND A(6) AND D(8).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(0) AND NOT A(1) AND A(6) AND D(8).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(0) AND NOT A(1) AND A(6) AND NOT D(8).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
IDE_BASEADR_T(1) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(1) AND NOT A(1) AND A(6) AND NOT D(9).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT IDE_BASEADR(1))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(1) AND NOT A(1) AND A(6) AND D(9).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(1) AND NOT A(1) AND A(6) AND D(9).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(1) AND NOT A(1) AND A(6) AND NOT D(9).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
IDE_BASEADR_T(2) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(2) AND NOT A(1) AND A(6) AND NOT D(10).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(2) AND NOT A(1) AND A(6) AND NOT D(10).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT IDE_BASEADR(2))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(2) AND NOT A(1) AND A(6) AND D(10).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(2) AND NOT A(1) AND A(6) AND D(10).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
IDE_BASEADR_T(3) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(3) AND NOT A(1) AND A(6) AND NOT D(11).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(3) AND NOT A(1) AND A(6) AND NOT D(11).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT IDE_BASEADR(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(3) AND NOT A(1) AND A(6) AND D(11).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(3) AND NOT A(1) AND A(6) AND D(11).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
IDE_BASEADR_T(4) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(4) AND NOT A(1) AND A(6) AND NOT D(12).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT IDE_BASEADR(4))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(4) AND NOT A(1) AND A(6) AND D(12).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(4) AND NOT A(1) AND A(6) AND D(12).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(4) AND NOT A(1) AND A(6) AND NOT D(12).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
IDE_BASEADR_T(5) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(5) AND NOT A(1) AND A(6) AND NOT D(13).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT IDE_BASEADR(5))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(5) AND NOT A(1) AND A(6) AND D(13).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(5) AND NOT A(1) AND A(6) AND D(13).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(5) AND NOT A(1) AND A(6) AND NOT D(13).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
IDE_BASEADR_T(6) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(6) AND NOT A(1) AND A(6) AND NOT D(14).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT IDE_BASEADR(6))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(6) AND NOT A(1) AND A(6) AND D(14).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(6) AND NOT A(1) AND A(6) AND D(14).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(6) AND NOT A(1) AND A(6) AND NOT D(14).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
IDE_BASEADR_T(7) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(7) AND NOT A(1) AND A(6) AND NOT D(15).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT IDE_BASEADR(7))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(7) AND NOT A(1) AND A(6) AND D(15).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT IDE_BASEADR(7) AND NOT A(1) AND A(6) AND D(15).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(2) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	IDE_BASEADR(7) AND NOT A(1) AND A(6) AND NOT D(15).PIN AND NOT LDS AND DS_D AND A(3)));


IDE_CS(0) <= NOT A(12);


IDE_CS(1) <= NOT A(13);

FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,IDE_ENABLE_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
IDE_ENABLE_D <= ((RESET AND NOT IDE_ENABLE)
	OR (NOT AS AND NOT RW AND RESET AND ide));


IDE_R <= NOT ((NOT AS AND NOT IDE_R_S));

FDCPE_IDE_R_S: FDCPE port map (IDE_R_S,IDE_R_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
IDE_R_S_D <= (NOT AS AND RW AND RESET AND ide AND NOT IDE_ENABLE);


IDE_W <= NOT ((NOT AS AND NOT IDE_W_S));

FDCPE_IDE_W_S: FDCPE port map (IDE_W_S,IDE_W_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
IDE_W_S_D <= (NOT AS AND NOT RW AND RESET AND ide);


INT_OUT_I <= '0';
INT_OUT <= INT_OUT_I when INT_OUT_OE = '1' else 'Z';
INT_OUT_OE <= '0';

FTCPE_LAN_BASEADR0: FTCPE port map (LAN_BASEADR(0),LAN_BASEADR_T(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
LAN_BASEADR_T(0) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(0) AND NOT A(1) AND A(6) AND NOT D(8).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT LAN_BASEADR(0))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(0) AND NOT A(1) AND A(6) AND D(8).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(0) AND NOT A(1) AND A(6) AND D(8).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(0) AND NOT A(1) AND A(6) AND NOT D(8).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_LAN_BASEADR1: FTCPE port map (LAN_BASEADR(1),LAN_BASEADR_T(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
LAN_BASEADR_T(1) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(1) AND NOT A(1) AND A(6) AND NOT D(9).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT LAN_BASEADR(1))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(1) AND NOT A(1) AND A(6) AND D(9).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(1) AND NOT A(1) AND A(6) AND D(9).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(1) AND NOT A(1) AND A(6) AND NOT D(9).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_LAN_BASEADR2: FTCPE port map (LAN_BASEADR(2),LAN_BASEADR_T(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
LAN_BASEADR_T(2) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(2) AND NOT A(1) AND A(6) AND NOT D(10).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT LAN_BASEADR(2))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(2) AND NOT A(1) AND A(6) AND D(10).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(2) AND NOT A(1) AND A(6) AND D(10).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(2) AND NOT A(1) AND A(6) AND NOT D(10).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_LAN_BASEADR3: FTCPE port map (LAN_BASEADR(3),LAN_BASEADR_T(3),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
LAN_BASEADR_T(3) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(3) AND NOT A(1) AND A(6) AND NOT D(11).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT LAN_BASEADR(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(3) AND NOT A(1) AND A(6) AND D(11).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(3) AND NOT A(1) AND A(6) AND D(11).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(3) AND NOT A(1) AND A(6) AND NOT D(11).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_LAN_BASEADR4: FTCPE port map (LAN_BASEADR(4),LAN_BASEADR_T(4),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
LAN_BASEADR_T(4) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(4) AND NOT A(1) AND A(6) AND NOT D(12).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(4) AND NOT A(1) AND A(6) AND NOT D(12).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT LAN_BASEADR(4))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(4) AND NOT A(1) AND A(6) AND D(12).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(4) AND NOT A(1) AND A(6) AND D(12).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_LAN_BASEADR5: FTCPE port map (LAN_BASEADR(5),LAN_BASEADR_T(5),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
LAN_BASEADR_T(5) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(5) AND NOT A(1) AND A(6) AND NOT D(13).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(5) AND NOT A(1) AND A(6) AND NOT D(13).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT LAN_BASEADR(5))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(5) AND NOT A(1) AND A(6) AND D(13).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(5) AND NOT A(1) AND A(6) AND D(13).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_LAN_BASEADR6: FTCPE port map (LAN_BASEADR(6),LAN_BASEADR_T(6),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
LAN_BASEADR_T(6) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(6) AND NOT A(1) AND A(6) AND NOT D(14).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(6) AND NOT A(1) AND A(6) AND NOT D(14).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT LAN_BASEADR(6))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(6) AND NOT A(1) AND A(6) AND D(14).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(6) AND NOT A(1) AND A(6) AND D(14).PIN AND NOT LDS AND DS_D AND A(3)));

FTCPE_LAN_BASEADR7: FTCPE port map (LAN_BASEADR(7),LAN_BASEADR_T(7),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
LAN_BASEADR_T(7) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(7) AND NOT A(1) AND A(6) AND NOT D(15).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	LAN_BASEADR(7) AND NOT A(1) AND A(6) AND NOT D(15).PIN AND NOT LDS AND DS_D AND A(3))
	OR (NOT RESET AND NOT LAN_BASEADR(7))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(7) AND NOT A(1) AND A(6) AND D(15).PIN AND NOT UDS AND DS_D AND A(3))
	OR (NOT AS AND NOT RW AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND SHUT_UP(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND 
	NOT LAN_BASEADR(7) AND NOT A(1) AND A(6) AND D(15).PIN AND NOT LDS AND DS_D AND A(3)));


LAN_CFG_I(1) <= '0';
LAN_CFG(1) <= LAN_CFG_I(1) when LAN_CFG_OE(1) = '1' else 'Z';
LAN_CFG_OE(1) <= '0';


LAN_CFG_I(2) <= '0';
LAN_CFG(2) <= LAN_CFG_I(2) when LAN_CFG_OE(2) = '1' else 'Z';
LAN_CFG_OE(2) <= '0';


LAN_CFG_I(3) <= '0';
LAN_CFG(3) <= LAN_CFG_I(3) when LAN_CFG_OE(3) = '1' else 'Z';
LAN_CFG_OE(3) <= '0';


LAN_CFG_I(4) <= '0';
LAN_CFG(4) <= LAN_CFG_I(4) when LAN_CFG_OE(4) = '1' else 'Z';
LAN_CFG_OE(4) <= '0';

FDCPE_LAN_CS: FDCPE port map (LAN_CS,LAN_CS_D,NOT AS,NOT ide/ide_RSTF__$INT,'0');
LAN_CS_D <= ((SHUT_UP(0))
	OR (EXP42_.EXP)
	OR (LAN_BASEADR(4) AND NOT A(20))
	OR (LAN_BASEADR(5) AND NOT A(21))
	OR (NOT LAN_BASEADR(5) AND A(21))
	OR (LAN_BASEADR(7) AND NOT A(23))
	OR (NOT LAN_BASEADR(7) AND A(23))
	OR (LAN_RD_OBUF.EXP)
	OR (LAN_BASEADR(0) AND NOT A(16))
	OR (NOT LAN_BASEADR(0) AND A(16))
	OR (LAN_BASEADR(1) AND NOT A(17))
	OR (NOT LAN_BASEADR(1) AND A(17))
	OR (NOT LAN_BASEADR(4) AND A(20))
	OR (LAN_BASEADR(6) AND NOT A(22))
	OR (NOT LAN_BASEADR(6) AND A(22)));


LAN_RD <= (NOT AS AND LAN_RD_S);

FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
LAN_RD_S_D <= ((RW AND LAN_CS AND NOT UDS)
	OR (RW AND LAN_CS AND NOT LDS));


LAN_WRH <= (NOT AS AND LAN_WRH_S);

FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
LAN_WRH_S_D <= (NOT RW AND LAN_CS AND NOT UDS);


LAN_WRL <= (NOT AS AND LAN_WRL_S);

FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
LAN_WRL_S_D <= (NOT RW AND LAN_CS AND NOT LDS);


OVR_I <= '0';
OVR <= OVR_I when OVR_OE = '1' else 'Z';
OVR_OE <= (NOT AS AND ide);


OWN_I <= '0';
OWN <= OWN_I when OWN_OE = '1' else 'Z';
OWN_OE <= NOT SLAVE_OBUF__$INT;


ROM_B(0) <= '0';


ROM_B(1) <= '0';


ROM_OE <= NOT ((NOT AS AND NOT ROM_OE_S));

FDCPE_ROM_OE_S: FDCPE port map (ROM_OE_S,ROM_OE_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
ROM_OE_S_D <= (NOT AS AND RW AND RESET AND ide AND IDE_ENABLE);

FDCPE_SHUT_UP0: FDCPE port map (SHUT_UP(0),SHUT_UP_D(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
SHUT_UP_D(0) <= ((NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT UDS AND 
	DS_D AND A(3))
	OR (RESET AND NOT SHUT_UP(0))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT LDS AND 
	DS_D AND A(3)));

FDCPE_SHUT_UP1: FDCPE port map (SHUT_UP(1),SHUT_UP_D(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
SHUT_UP_D(1) <= ((RESET AND NOT SHUT_UP(1))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT UDS AND 
	DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND 
	AUTO_CONFIG_DONE(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT LDS AND 
	DS_D AND A(3)));

FDCPE_SHUT_UP2: FDCPE port map (SHUT_UP(2),SHUT_UP_D(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
SHUT_UP_D(2) <= ((RESET AND NOT SHUT_UP(2))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT UDS AND 
	DS_D AND A(3))
	OR (NOT AS AND NOT RW AND RESET AND NOT A(2) AND AUTO_CONFIG_DONE(1) AND 
	NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND NOT LDS AND 
	DS_D AND A(3)));


SHUT_UP(2)/SHUT_UP(2)_CLKF <= C1
	 XOR 
SHUT_UP(2)/SHUT_UP(2)_CLKF <= C3;


SLAVE <= ((AS)
	OR (NOT LAN_CS AND NOT ide AND NOT autoconfig AND CP_CS));


SLAVE_OBUF__$INT <= ((AS)
	OR (NOT LAN_CS AND NOT ide AND NOT autoconfig AND CP_CS));

FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,NOT AS,NOT ide/ide_RSTF__$INT,'0');
autoconfig_D <= ((NOT AUTO_CONFIG_DONE(1) AND NOT CFIN AND NOT A(18) AND NOT A(17) AND 
	NOT A(16) AND A(23) AND A(22) AND A(21) AND A(19) AND NOT A(20))
	OR (NOT AUTO_CONFIG_DONE(0) AND NOT CFIN AND NOT A(18) AND NOT A(17) AND 
	NOT A(16) AND A(23) AND A(22) AND A(21) AND A(19) AND NOT A(20)));

FDCPE_ide: FDCPE port map (ide,ide_D,NOT AS,NOT ide/ide_RSTF__$INT,'0');
ide_D <= ((SHUT_UP(2))
	OR (EXP29_.EXP)
	OR (IDE_BASEADR(0) AND NOT A(16))
	OR (NOT IDE_BASEADR(0) AND A(16))
	OR (IDE_BASEADR(1) AND NOT A(17))
	OR (IDE_BASEADR(2) AND NOT A(18))
	OR (NOT IDE_BASEADR(2) AND A(18))
	OR (NOT IDE_BASEADR(1) AND A(17))
	OR (IDE_BASEADR(6) AND NOT A(22))
	OR (NOT IDE_BASEADR(6) AND A(22))
	OR (IDE_BASEADR(7) AND NOT A(23))
	OR (NOT IDE_BASEADR(7) AND A(23))
	OR (IDE_BASEADR(3) AND NOT A(19))
	OR (NOT IDE_BASEADR(3) AND A(19)));


ide/ide_RSTF__$INT <= (RESET AND BERR);

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95288XL-10-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 VCC                              73 VCC                           
  2 D<0>                             74 KPR                           
  3 A_LAN<1>                         75 AUTOBOOT_OFF                  
  4 A_LAN<0>                         76 LAN_WRL                       
  5 A_LAN<3>                         77 KPR                           
  6 A_LAN<2>                         78 KPR                           
  7 A_LAN<5>                         79 KPR                           
  8 VCC                              80 AS                            
  9 A_LAN<4>                         81 UDS                           
 10 A_LAN<7>                         82 LDS                           
 11 A_LAN<6>                         83 RW                            
 12 LAN_CFG<1>                       84 VCC                           
 13 LAN_CFG<3>                       85 DTACK                         
 14 D<6>                             86 A<23>                         
 15 D<3>                             87 A<22>                         
 16 D<7>                             88 A<21>                         
 17 D<1>                             89 GND                           
 18 GND                              90 GND                           
 19 D<8>                             91 A<20>                         
 20 D<5>                             92 A<19>                         
 21 D<4>                             93 KPR                           
 22 IDE_CS<0>                        94 A<18>                         
 23 IDE_CS<1>                        95 A<17>                         
 24 IDE_A<0>                         96 KPR                           
 25 IDE_A<2>                         97 A<16>                         
 26 IDE_A<1>                         98 BERR                          
 27 IDE_R                            99 GND                           
 28 IDE_W                           100 OVR                           
 29 GND                             101 KPR                           
 30 KPR                             102 C3                            
 31 KPR                             103 C1                            
 32 INT_OUT                         104 CFIN                          
 33 IDE_WAIT                        105 CFOUT                         
 34 CP_CS                           106 SLAVE                         
 35 ROM_OE                          107 OWN                           
 36 GND                             108 GND                           
 37 VCC                             109 VCC                           
 38 KPR                             110 LAN_CFG<4>                    
 39 D<2>                            111 KPR                           
 40 D<9>                            112 DQ<15>                        
 41 D<10>                           113 DQ<13>                        
 42 VCC                             114 GND                           
 43 D<11>                           115 DQ<11>                        
 44 D<12>                           116 DQ<9>                         
 45 D<13>                           117 DQ<1>                         
 46 D<14>                           118 DQ<0>                         
 47 GND                             119 DQ<3>                         
 48 D<15>                           120 DQ<2>                         
 49 A<5>                            121 DQ<5>                         
 50 A<4>                            122 TDO                           
 51 A<6>                            123 GND                           
 52 A<3>                            124 DQ<4>                         
 53 A<7>                            125 DQ<7>                         
 54 A<2>                            126 DQ<6>                         
 55 VCC                             127 VCC                           
 56 A<8>                            128 DQ<8>                         
 57 A<1>                            129 DQ<10>                        
 58 A<9>                            130 DQ<12>                        
 59 A<10>                           131 DQ<14>                        
 60 A<11>                           132 LAN_WRH                       
 61 A<12>                           133 LAN_CS                        
 62 GND                             134 LAN_RD                        
 63 TDI                             135 LAN_CFG<2>                    
 64 A<13>                           136 A_LAN<13>                     
 65 TMS                             137 A_LAN<12>                     
 66 A<14>                           138 A_LAN<10>                     
 67 TCK                             139 A_LAN<11>                     
 68 ROM_B<0>                        140 A_LAN<8>                      
 69 ROM_B<1>                        141 VCC                           
 70 CP_WE                           142 A_LAN<9>                      
 71 CP_RD                           143 RESET                         
 72 GND                             144 GND                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95288xl-10-TQ144
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 35